Principal Engineer Memory Architect
About The Position
MaxLinear is seeking a Principal Engineer Memory Architect to join our team. In this role, you will focus on the following: Design, define, evaluate, and optimize memory intellectual property across advanced technology nodes. Leverage your memory architecture expertise, circuit-level understanding, and system-level awareness to deliver high-performance, power-efficient, area-optimized, and reliable memory solutions for SoC integration. Work closely with IP and SoC teams to provide technical direction for memory IP roadmaps, architecture selection, compiler evaluation, and trade-off decisions involving PPA and robustness. Own the design and optimization of memory architectures, based on SRAMs, ROMs, and register files, using memory compilers or custom designs. Deliver competitive memory IP solutions and enabling seamless integration into SoCs. Collaborate with cross-functional engineering teams and external IP vendors, and developing scalable QA methodologies, automation flows, and verification frameworks for consistent memory IP evaluation.
Requirements
- Deep understanding of embedded SRAM and register-file architectures, including bit-cell fundamentals, array layout considerations, and PPA trade-offs
- Strong knowledge of low-power techniques, read/write assist techniques, design stability and robustness, design margining and power integrity considerations
- Experience analyzing memory behavior across PVT corners and evaluating timing, reliability, signal integrity, and SoC-level trade-offs
- Strong understanding of memory compiler flows and verification methodologies, with the ability to assess both compiled and custom memory solutions
- Excellent communication skills and ability to collaborate effectively across multidisciplinary teams and influence technical decisions at both strategic and hands-on levels
- BS in Electrical Engineering or related + 9 years of experience, or MS + 7 years of experience, or Ph.D. + 4 years of experience
Nice To Haves
- Proficiency with EDA and analysis tools HSPICE, Spectre, Python, and related memory verification or modeling environments
- Familiarity with SoC design flows and interactions among memory IP, standard cells, I/O libraries, clocking, system buses, and interface protocols
- Familiarity with ROMs, flash memories, OTPs is a plus
- Understanding of advanced-node scaling, PVT variation impacts, memory behavior across corners, and silicon validation practices
- Familiarity with transistor-level circuit design and analysis, and experience using IC design or simulation tools such as HSPICE, Spectre, or Cadence Virtuoso, is a plus
- Experience with QA methodologies, validation frameworks, technical roadmaps
Responsibilities
- Design, define, evaluate, and optimize memory intellectual property across advanced technology nodes
- Leverage memory architecture expertise, circuit-level understanding, and system-level awareness to deliver high-performance, power-efficient, area-optimized, and reliable memory solutions for SoC integration
- Work closely with IP and SoC teams to provide technical direction for memory IP roadmaps, architecture selection, compiler evaluation, and trade-off decisions involving PPA and robustness
- Own the design and optimization of memory architectures, based on SRAMs, ROMs, and register files, using memory compilers or custom designs
- Deliver competitive memory IP solutions and enabling seamless integration into SoCs
- Collaborate with cross-functional engineering teams and external IP vendors
- Develop scalable QA methodologies, automation flows, and verification frameworks for consistent memory IP evaluation
Benefits
- health care benefits
- 401k savings plan
- Employee Stock Purchase Plan (ESPP)
- paid time off
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What This Job Offers
Job Type
Full-time
Career Level
Principal
Education Level
Ph.D. or professional degree
