Staff Engineer, GPU Memory Architect

Samsung•San Diego, CA

3d•Onsite

About The Position

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are building a center of excellence for Intellectual Property (IP) that powers high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Join us to shape the future of GPU memory systems! As a Staff GPU Memory Architect, you will drive the definition, architecture, and implementation of next‑generation GPU memory subsystems and on‑chip interconnects for Samsung’s Exynos chipset. In this mid-to-senior individual contributor role, you will directly influence performance, power, and area (PPA) of GPUs used in premium mobile and emerging AI workloads.

Requirements

6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
6+ years of experience in GPU architecture, design, or development, with a focus on high-performance, low-power designs.
Knowledge of machine learning or graphics and GPU pipelines, hardware design, and computer architecture.
Proven track record of analyzing and optimizing memory subsystems to improve PPA.
Deep knowledge of memory hierarchies (caches, shared memory, SRAM, DRAM), bandwidth‑allocation policies, coherence protocols, and on‑chip interconnect.
Strong background in low‑power design techniques and performance‑modeling tools (analytical models, RTL‑level simulation).
Experience with emerging GPU workloads such as ray tracing, AI/ML inference, and AR/VR, and ability to translate algorithmic requirements into memory‑system specifications.
Excellent communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.

Nice To Haves

Experience with CPU, NPU, or other complex processing units, such as ARM, x86, or RISC-V.
Experience in performance modeling, statistical analysis, and hardware‑software co‑design for AI accelerators.

Responsibilities

Lead architecture studies and micro‑architecture development for GPU global memory hierarchies, cache structures, and high‑bandwidth memory interfaces.
Define and champion innovative features for next‑generation GPU memory and on‑chip interconnect subsystems, targeting optimal PPA.
Collaborate with cross‑functional teams (GPU pipeline, CPU/NPU architects, silicon validation, physical design, software) to ensure seamless integration of memory blocks into the overall system‑on‑chip (SoC).
Build and maintain performance‑power‑area models; run architectural trade‑studies for emerging workloads such as ray‑tracing, AI inference, and large‑scale graphics.
Drive data‑driven decision making by producing architectural roadmaps, design specifications, and validation plans.