SoC Infrastructure/NoC, Power & Performance Validation Engineer

Qualcomm•San Diego, CA
•$121,800 - $182,600

About The Position

Qualcomm's validation team is part of the central Global SoC digital hardware organization responsible for the overall quality of the SoC silicon. The validation team works closely with architects, designers, verification engineers, software engineers, and customers. The team is currently seeking a candidate specifically for SOC Infrastructure/NoC, Power and Performance Validation in pre-silicon emulation and post-silicon. The candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture, performance and power.

Requirements

  • Experience in embedded systems/expertise in C, C++, Python and assembly languages
  • Familiarity in debug tools including JTAG and kernel debuggers
  • Structured program development concepts

Responsibilities

  • SOC Bandwidth, QoS, Latency and Throughput analysis
  • Interconnect architectures - NoCs,AXI, AHB etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage
  • Solid expertise in various FIFO designs and related performance/functionality aspects
  • Come up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored in
  • System Low power modes
  • Dynamic clock and voltage scaling operations
  • Interrupt architecture
  • Debug architecture - interactions with JTAG based debuggers, state dump scripts
  • Performance monitor architecture
  • Thorough understanding of CPU and DDR concepts, Mumtimedia, GPU, Peripheral,
  • Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM
  • Design and Implementation of drivers and test content
  • Debugging low level software and hardware issues
  • Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design
  • Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation
  • Experience leveraging Generative AI technologies for optimizing workflows

Benefits

  • competitive annual discretionary bonus program
  • opportunity for annual RSU grants
  • highly competitive benefits package
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