SoC Hardware Characterization Lead, Power and Performance

Google•San Diego, CA

2d•$240,000 - $333,000

About The Position

Be part of a team developing custom silicon solutions for Google’s direct-to-consumer products. Google’s team combines AI, software, and hardware to research, design, and develop technologies intended to make computing faster, seamless, and more powerful and people’s lives better through technology. The SoC Hardware Characterization Lead is the principal technical owner bridging custom silicon and consumer hardware software teams. The role leads end-to-end post-silicon validation, debugging, and optimization across voltage, frequency, and power-management architectures. It architects scalable hardware-software frameworks for platform-level power and performance optimization, improves SoC energy efficiency, and ensures system stability for product launch. The position serves as a central technical authority across chip design, architecture, product test engineering, and system software; aligns cross-functional partners; streamlines manufacturing test screens while safeguarding quality metrics; and leads an engineering team through complex debugging to deliver launch-critical milestones. Individual pay is determined by job-related skills, experience, and relevant education or training. The listed US compensation is $240,000–$333,000 USD, plus a 25% bonus target, equity, and benefits.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
15 years of experience with power management or low-power design/methodology.
Experience navigating the full product silicon/SoC delivery cycle, from initial architecture definition through post-silicon productization.
Experience with low-power architectures or advanced power optimization techniques.

Nice To Haves

Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture or power/performance analysis.
Experience with product characterization, DVFS governor, power analysis, thermal management, peak power management, in-rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power-aware floorplanning, battery technology, concurrency management, or thermal management.
Exceptional leadership and persuasion skills, with demonstrated ability to influence cross-functional roadmaps and drive ROI-based technical decisions.

Responsibilities

Bridge chip design, architecture, product engineering, and system software to architect scalable silicon-software frameworks, accelerate power-management deliverables, and drive continuous power, performance, and platform-stability optimizations.
Direct end-to-end post-silicon validation, characterization, and debugging across voltage, frequency, and power architectures; ensure physical silicon behavior aligns with architectural intent and drive cross-functional alignment on feature value and product trade-offs.
Partner with engineering stakeholders to optimize manufacturing test processes and production screening capabilities, fine-tune voltage margins, and safeguard product quality standards and defect targets (DPPM).
Mentor and guide an engineering team focused on complex system characterization, including operating limits (Fmax and Vmin), energy efficiency, and root-cause hardware stability debugging.
Drive the long-term technology roadmap for sensing subsystems (voltage, current, and temperature) and hardware trigger mechanisms to address rising current densities and industry trends.