Silicon Compute RTL Design Manager, Machine Learning

Google•Sunnyvale, CA

4d•$256,000 - $278,000

About The Position

The Silicon Compute RTL Design Manager will develop high-performance, low-power hardware for Google Tensor Processing Units (TPUs), which power demanding AI/ML applications. The role focuses on IP development for Compute Cores and on verifying complex digital designs, particularly TPU architecture and integration within AI/ML-driven systems. The manager works with architects to assess architectural feasibility, establish timing goals, and explore trade-offs for physical design closure. The role also partners with software teams to understand and implement clocking and power-management requirements, and collaborates with cross-functional engineering teams throughout the development cycle. The position is part of Google's AI and Infrastructure team, which develops AI and infrastructure capabilities, computing platforms, and hardware and software for Google products and services.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience with chip design, ASIC digital design, and SystemVerilog.
8 years of experience in computer architecture and register-transfer level (RTL).
3 years of experience in people management and developing employees.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Knowledge of high-performance and low-power design techniques.
Knowledge of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design.

Responsibilities

Lead, mentor, and manage a team of RTL Design Engineers working on IP development for Compute Cores.
Provide technical leadership and model design best practices, including micro-architecture specifications, design reviews, code reviews, and design methodology.
Serve as the primary point of contact for design-related project activities.
Work with Architecture and System Design teams on architecture definition, IP area estimation, power optimization, and performance enhancements.
Collaborate with Verification, Design for Test, Physical Design, and Software teams to create design plans and present project status throughout development.
Drive improvements in design methodologies, processes, and quality-control measures.
Work with architects to assess architectural feasibility, establish timing design goals, and explore trade-offs for physical design closure.
Work with software teams to understand and implement clocking and power-management requirements.