Signal/Power Integrity Hardware Engineer Technical Lead (Onsite)

Cisco•San Jose, CA

1d•Onsite

About The Position

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. The Cisco Service Provider SI team is seeking a Technical Lead, Signal/Power Integrity Engineer for the design and analysis of high-speed interconnects and power distribution networks. As a member of the Service Provider SI team, you will help develop the next generations of Cisco Switch and Router products, participating in the definition and design of current and next-generation ASICs, packages, printed circuit boards (PCBs), and system interconnects. You will be working in a larger team, collaborating closely with system architects, ASIC engineers, package engineers, and versatile and knowledgeable SI/PI engineers in the creation of next-generation networking products.

Requirements

Bachelors in Electrical Engineering + 7 years of related experience, or Masters in Electrical Engineering + 5 years of related experience, or PhD in Electrical Engineering + 2 years of related experience.
Experience applying EE fundamentals, EM theory, and coupling mechanisms in circuit or system design, analysis, or troubleshooting.
Experience with transmission line theory, channel modeling, and signal/power integrity, including simulation and analysis.
Lab and measurement experience to include configuring and interpreting measurements from VNA, TDR, and oscilloscopes.

Nice To Haves

Tools knowledge with tools such as HFSS, ADS, MATLAB, Cadence PowerSI/DC, Allegro, Simbeor, and HSpice.
Experience with 3-D field solvers and PI (Power Integrity) simulation tools such as PowerSI/DC.
Self-motivation, collaboration, effective communication, and a desire to innovate.
Working experience with high-speed NRZ and PAM4 SerDes, as well as high-speed PCB/package development and PI analysis.
Knowledge of optical transceiver module types, form factors, and requirements.
Masters or PhD in Electrical Engineering.

Responsibilities

High-speed link modeling and simulation, including high-speed I/O, IC package, and system interconnections.
Modeling and analyzing power delivery networks.
Electromagnetic modeling of complex 3-dimensional structures.
Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs.
Write signal integrity design guidelines, test plans, and test reports.
Decide appropriate PCB material, stack-up, and work with vendors to address any DFM (Design for Manufacturability) issues.
Support prototype function bring-up, validation, and troubleshooting.
Work closely with other hardware function teams including HW design, eCAD, Mechanical, Power, EMC, and Diagnostics to deliver first-class products.
Provide technical leadership and mentorship to junior SI/PI engineers, fostering skill development and best practices within the team.
Drive the definition, implementation, and continuous improvement of advanced SI/PI methodologies, simulation flows, and design processes.
Contribute to the overall SI/PI technology roadmap, evaluating new tools, techniques, and design approaches to maintain a competitive edge.
Lead the investigation and resolution of highly complex, system-level signal and power integrity challenges that span multiple domains (ASIC, package, PCB, system).
Lead comprehensive SI/PI design reviews, providing expert guidance and ensuring adherence to stringent performance and reliability targets.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt employees)
flexible vacation time off program (exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses
performance-based incentive pay