This role involves supporting high data rate SerDes applications up to 400G systems. The engineer will be responsible for system-level Signal and Power Integrity design trade-offs and debug, collaborating with package, PCB, and silicon designers on measurement-simulation correlation projects. The position requires developing models using electromagnetic field solvers, understanding laminate design and fabrication, and evaluating material and connector solutions. The engineer will simulate schematic models in Keysight ADS, ensure model accuracy, and perform VNA/TDR measurements for correlation with simulations. Feedback from these investigations will be used to improve best practices. High-fidelity lab measurements will be captured for correlation and debug. The role also involves understanding and applying high-speed data communications principles, transmission-line and electromagnetic-field theory, numerical analysis, VNA/TDR measurements, and simulators for serial data links. Experience with oscilloscopes, spectrum analyzers, and optical oscilloscopes is expected. The engineer will work in either time or frequency domain, analyze phase noise, and perform jitter sensitivity measurements. Project management, documentation, and clear communication of complex concepts are essential. The role requires defining requirements for ASIC package and PCB designs, collaborating with engineers to meet System SI requirements while balancing objectives, and performing pre-layout and post-layout modeling and simulation. The engineer will document and deliver SI models, support customer analysis, and understand optical/electrical engine concepts and optical channel impairments. Power Integrity concepts include PDN impedance analysis, ultra-low impedance measurements, capacitor performance, and PDN simulations.
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Job Type
Full-time
Career Level
Senior