This role involves supporting high data rate SerDes applications up to 400G systems, focusing on system-level Signal and Power Integrity design trade-offs and debug. The engineer will collaborate with package, PCB, and silicon designers on measurement-simulation correlation projects, develop models using electromagnetic field solvers (primarily Ansys HFSS and electronic suite), and evaluate material and connector solutions. The position requires simulating schematic models in Keysight ADS, understanding model accuracy trade-offs, and performing VNA/TDR measurements (50GHz+) for correlation with models and simulations. Feedback from these correlation investigations will be used to improve best practices. The role also involves capturing high-fidelity lab measurements, using oscilloscopes, spectrum analyzers, and optical oscilloscopes, and applying knowledge of high-speed data communications, transmission-line theory, electromagnetic-field theory, numerical analysis, VNA/TDR measurements, statistical simulators, and various signal integrity metrics. Project management, documentation, and effective communication of complex concepts are also key aspects of this role. The engineer will determine and document requirements for ASIC package and PCB designs, collaborate with Package and PCB Engineers to fulfill System SI requirements while balancing objectives, and perform pre-layout and post-layout modeling and simulation. The role includes documenting and delivering SI models, supporting customer analysis and debug efforts, and understanding optical/electrical engine concepts, CWDM, OMA, and optical channel impairments. Power Integrity concepts include PDN impedance analysis and design, ultra-low impedance measurements, SMT capacitor performance, and PDN simulations using CPA and/or SI-Wave.
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Job Type
Full-time
Career Level
Senior