Signal Integrity Engineer, Infrastructure Hardware

Meta•Austin, TX

1d•$118,000 - $170,000

About The Position

Meta's infrastructure hardware team is seeking a Signal Integrity Engineer to drive the design and validation of high-speed interconnects across Meta's data center platforms. In this role, you will contribute to signal integrity design, analysis, and validation for next-generation AI, networking, and compute platforms, enabling reliable high-speed data transmission across Ethernet, PCIe, DDR, and optical interconnect interfaces. You will contribute to new and emerging technologies, participate in platform architecture decisions, and collaborate closely with industry partners and hardware design team to deliver infrastructure at the scale Meta's global data centers demand.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience
2+ years of experience in signal integrity engineering for high-speed digital systems, including board-level and system-level SI/PI analysis
Programming experience in test/measurement automation and/or simulation

Nice To Haves

Experience with PCB board level design, layout, and validation
Experience collaborating on SerDes bring-up, equalization tuning, and compliance testing for next-generation interface standards
Experience with advanced PCB materials, HDI materials, and evolving interconnect technologies
Familiarity with IBIS-AMI modeling, channel simulation automation scripting, and statistical eye analysis methodologies
Experience with lab correlation and validation activities, including TDR, VNA, and oscilloscope-based measurements, to verify simulation accuracy and characterize channel performance

Responsibilities

Support the development of next-generation SI/PI solutions across a broad range of Meta platforms, including AI, network, and compute systems
Perform signal integrity simulations, implementation, validation, and test methodologies at the board and system levels using industry-standard tools such as HSpice, ADS, or Sigrity to validate channel performance and margins
Develop and maintain channel models, IBIS-AMI models, and S-parameter extraction workflows for board-level and system-level SI analysis including end-to-end electrical-optical-electrical channels
Collaborate with design and manufacturing teams to define stack-up requirements, routing constraints, via structures, and impedance targets for multi-layer high-speed designs
Drive lab correlation and validation activities, including TDR, VNA, and oscilloscope-based measurements, to verify simulation accuracy and characterize channel performance
Partner with silicon vendors and internal ASIC teams to evaluate PHY specifications, equalization parameters, and link training behavior for new interface standards