Senior Staff Digital Design Engineer

Marvell Technology • Ottawa, ON

61d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact Optical PHY BU develops cutting-edge optical Ethernet Transceiver ASICs. Current online working and meetings that are through mediums such as Zoom and Webex are all based on cloud services. In order to respond to the dramatically increased demands of cloud-based connection capability, major cloud computing companies urgently demand faster and more secure internet connection components. One critical part of that component includes the optical ethernet transceiver ASICs. As a member of a digital hardware development team, the candidate will be assisting in chip design, verification, supporting back-end teams and timing closure. What You Can Expect Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification. Develop high speed data path and control plane RTL blocks using Verilog, synthesis and backend resources Integrate vendor IP and support Well versed with the complete ASIC flow from micro-architecture to customer deployment Post-silicon debug and correlation Develop ASIC specification and micro-architecture of signal processing and communications algorithms Assist in design automation of various aspects of the CAD EDA flow.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience.
• 5+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 16nm or smaller technology.
• Familiarity with the entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
• Experience with Verilog, System Verilog, Python, and Unix Shell.
• Experience in both RTL development (block and subsystem level) and gate level verification and debug.
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
• Effective communication and presentation skills and a team player

Responsibilities

• Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
• Develop high speed data path and control plane RTL blocks using Verilog, synthesis and backend resources
• Integrate vendor IP and support
• Well versed with the complete ASIC flow from micro-architecture to customer deployment
• Post-silicon debug and correlation
• Develop ASIC specification and micro-architecture of signal processing and communications algorithms
• Assist in design automation of various aspects of the CAD EDA flow.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level