Staff Digital Design Engineer

Kyocera International, Inc. (North America)•San Diego, CA

3h•Onsite

About The Position

The Staff Digital Design Engineer will contribute to the development of advanced phased array antenna modules and high-performance communication systems. This role combines system-level digital design involvement of Phase Array Antenna Modules with hands-on digital ASIC/SoC development, including RTL design, verification, subsystem integration, and silicon implementation support. The ideal candidate will have a strong background in digital design and SoC development, along with an interest in working across system, firmware, and physical design domains.

Requirements

RTL design using SystemVerilog (or Verilog)
Simulation, debugging, and verification workflows
Experience with SoC integration including processor subsystems, preferably RISC-V
Familiarity with embedded software interaction, including C programming
Experience with: Timing analysis and closure, Synthesis and backend design collaboration, ECO generation and implementation
Working knowledge of common hardware interfaces (SPI, QSPI, high-speed serial links)
Bachelor’s or Master’s degree in Electrical Engineering or related field
6 + years of experience in digital ASIC/SoC design
Strong problem-solving and debugging skills
Ability to work effectively in cross-functional teams
Clear communication and documentation skills
Interest in both system-level and implementation-level design challenges

Responsibilities

Design and implement digital subsystems for phased array and communication system applications
Develop high-quality RTL (SystemVerilog) for control and data path logic
Participate in system architecture and partitioning, collaborating with RF, firmware, and system teams
Integrate processor-based subsystems (e.g., RISC-V) into complex SoC designs
Collaborate with firmware teams supporting embedded software development (C)
Implement and support interfaces such as: SPI / QSPI, High-speed serial interfaces (e.g., JESD204B/C or similar)
Support verification activities and contribute to adoption of UVM and/or formal methodologies
Work closely with physical design teams to: Analyze and resolve timing issues, Support synthesis and place-and-route flows, Develop and implement engineering change orders (ECOs)
Participate in system bring-up, validation, and debug
Perform any other related duties as required or assigned.