Staff Digital Design Engineer

Marvell Technology•San Diego, CA

23h

About The Position

Join Marvell's Custom Compute Solutions Business Unit (CCSBU) as we establish our design presence in San Diego's thriving semiconductor ecosystem. This team will be responsible for delivering high‑quality customer silicon for advanced AI, XPU, and XPU‑Attach programs. By partnering closely with customers and internal stakeholders, the design center will enable Marvell’s most strategic and financially significant custom SoC initiatives, delivering differentiated solutions that reinforce Marvell’s position as a trusted partner for next‑generation compute platforms. This is a rare career opportunity. You're not joining an established local team - you'll be part of building one. You'll define the culture and shape the technical DNA of Marvell's San Diego design organization.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5+ years of related professional experience. Or Master’s/PhD in Computer Science, Electrical Engineering or related fields with 2-3+ years of experience.
Experience with SystemVerilog RTL coding techniques.
Experience in high speed, multiple clock domain designs
Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.
Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors
RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers
Excellent verbal and written communication
Discipline and rigor in documentation
Ability to work efficiently and influentially with team members across multiple sites
Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow

Nice To Haves

Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

Responsibilities

Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
Participate in the design development cycle, from RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
Schedule detailed reviews with cross-functional teams
Evaluate and participate in improving design and verification methodologies.