Senior Staff Digital Design Engineer

Impinj•Seattle, WA

1d•Hybrid

About The Position

Impinj is a leading RAIN RFID provider and Internet of Things pioneer. We’re inventing ways to connect every thing to the Internet — including retail apparel, retail general merchandise, healthcare items, automobile parts, airline baggage, food and much more. With more than 100 billion items connected to date, and multiple Fortune 500 enterprises around the world using our platform, we solve for a better understanding of our world. If it’s a thing, we’re working to connect it. Join Impinj and help us realize our vision of a boundless IoT— connecting trillions of everyday items to the Internet. The RAIN Reader IC (RIC) design group is part of the Impinj Silicon Engineering department and is responsible for the development of Impinj’s RIC products. Within the RIC Design group, the digital team owns the digital subsystems of these products, including the digital modem, the microcontroller subsystem, digital control loops, calibration engines, and the control and interface logic for analog IP. The team carries these designs from architecture and micro-architecture definition through RTL, verification, DFT, and timing closure to tapeout, post-silicon bring-up, and validation, partnering closely with chip architects, RF/analog designers, physical design, and CAD/EDA engineers and using state-of-the-art tools and methodologies. The team works to balance short-term goals needed to deliver products rapidly to market and long-term enhancements to methodologies and practices to enable future efficiencies.

Requirements

Bachelor’s degree in Computer Engineering, with 12 years of experience (or 8 years with MS or 5 years with a PhD) required.
12+ years of RTL design experience, including at least 2–3 full tapeout cycles preferably on mixed-signal or RF-integrated ICs.
Strong skills in digital logic design, micro-architecture definition, synthesis, and timing closure.
Proficiency in Verilog and SystemVerilog for RTL development, behavioral modeling, and verification.
Solid understanding of digital design methodologies including CDC analysis, clock gating, low-power design (UPF/CPF), and static timing analysis.
Experience with UVM-based verification, functional coverage, assertion-based verification, and DFT implementation (scan, MBIST, ATPG).
Scripting proficiency in Python, Perl, or UNIX shell for flow automation and design productivity.
Proven ability to lead technical workstreams, mentor junior engineers, and communicate effectively across analog, digital, and systems disciplines.

Responsibilities

Drive the digital design of Impinj's next-generation RAIN RFID Reader ICs from architecture through tapeout and silicon validation.
Develop micro-architectures, create executable models, and implement RTL for complex digital and mixed-signal IC subsystems.
Collaborate with chip architects and RF/analog engineers to partition and realize advanced mixed-signal architectures, including digital control loops, calibration engines, and interface logic for analog IP.
Partner with physical design and verification teams to ensure timing closure, signal integrity, and delivery of production-ready Reader ICs.
Define and implement DFT strategies — including scan insertion, BIST, and boundary scan — appropriate for mixed-signal Reader IC designs.
Work with CAD/EDA engineers to evolve Impinj's ASIC/SoC design flows, methodologies, and best practices.
Enhance existing RAIN RFID Reader products with new features, performance improvements, and power optimizations.
Support post-silicon bring-up and debug, correlating RTL and simulation results with lab measurements to validate design intent.