Senior Staff Engineer - SerDes Digital Design

Marvell Technology•Village of Woodbury, NY

13d

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products What You Can Expect ASIC design engineer responsible for planning and coordinating the design, verification, and evaluation of digital circuits in high-speed data communication ICs. The candidate will work closely with digital design, design verification, firmware, and analog design engineers to ensure that projects are completed on time and in high quality. The responsibilities include but are not limited to: Collaborate with Analog/DSP/DV/FW/AE teams to coordinate the delivery of competitive SerDes IP solutions for all the Marvell product lines Understand and improve the unique in-house design methodology and flow Provide support to the product teams for both pre and post silicon Lead the development and execution of RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications Work with cross-functional teams to define requirements, create schedules and budgets, manage risks, and communicate with stakeholders Develop and maintain relationships with key stakeholders Identify and mitigate risks to project success Track and report on analog mixed-signal IP development progress Continuously improve project execution processes

Requirements

Bachelor degree in Computer Science, Electrical Engineering or related fields and 5-15 years of related professional experience
Master degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience
Good personal communication skills and collaborative spirit
Strong work ethic and motivation to be part of a highly competent design team
Must be proficient in the following skills: Fundamental concepts in digital design, design verification, and timing closure (STA) in support of high-speed analog mixed-signal SerDes design
Concepts in physical and layout design
Excellent cross-discipline communication and interpersonal skills
Ability to work independently and as part of a team
Strong problem-solving and decision-making skills
Verilog coding

Nice To Haves

Experience with design flow and methodology
Experience with silicon validation support
Experience with power analysis and optimization
Strong Perl and Tcl scripting skill

Responsibilities

Collaborate with Analog/DSP/DV/FW/AE teams to coordinate the delivery of competitive SerDes IP solutions for all the Marvell product lines
Understand and improve the unique in-house design methodology and flow
Provide support to the product teams for both pre and post silicon
Lead the development and execution of RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications
Work with cross-functional teams to define requirements, create schedules and budgets, manage risks, and communicate with stakeholders
Develop and maintain relationships with key stakeholders
Identify and mitigate risks to project success
Track and report on analog mixed-signal IP development progress
Continuously improve project execution processes