Senior STA Signoff Methodology Engineer

NVIDIA•Austin, TX

10d•$168,000 - $310,500

About The Position

NVIDIA is seeking a Senior STA Signoff Methodology Engineer to develop sign-off strategies for GPUs, CPUs, LPUs, and SoCs. The role focuses on optimizing performance, yield, and reliability through modeling, analysis, and automation, with contributions across NVIDIA product lines and advanced technology nodes, including 3 nm and beyond. The engineer will run large-scale SPICE simulations and STA experiments, develop STA and place-and-route flows and recommendations for advanced-node physical effects, and collaborate with technology, physical-design, and timing teams on timing-signoff strategies. The position also involves building tools and methodologies to improve performance, predictability, and silicon reliability, working across STA, constraints, timing and power optimization, and using data analysis to improve STA-to-silicon correlation. The position requires an MS in Electrical or Computer Engineering, or equivalent experience, and 8 years of experience in ASIC design and timing. NVIDIA offers a competitive salary, equity, and benefits. The expected base salary is $168,000–$264,500 for Level 4 and $196,000–$310,500 for Level 5. Applications will be accepted at least until November 3, 2026.

Requirements

MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of experience in ASIC design and timing.
Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
Foundation in the mathematics and physics underlying electrical design.
Experience with low-power techniques, including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.
Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond.
Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus.
Strong communication skills and a collaborative working style.

Nice To Haves

Familiarity with 3D IC integration, die stacking and packaging, self-heating, and their impact on timing closure.
Strong data-analysis and modeling skills using Python, JMP, or similar platforms.
Proficiency in Tcl and Python; C++ experience is a plus.

Responsibilities

Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
Develop STA and PNR flows and recommendations that address aging, self-heating, thermal effects, IR drop, electromigration, and other advanced-node physical effects.
Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy timing-signoff strategies.
Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond standard EDA-tool capabilities.
Work across STA, constraints, and timing and power optimization.
Perform data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.