Senior Software Engineer – AI for RTL Design & Formal Verification
About The Position
Astera Labs is hiring a Senior Software Engineer for its AppliedAI organization, which develops connectivity infrastructure for AI and cloud data centers. The role focuses on developing and deploying AI-driven agents and applications to accelerate RTL and physical design, static analysis, and formal verification workflows. The ideal candidate brings software engineering and ASIC experience, exposure to digital or analog design or verification, and an interest in applying LLMs and agentic systems to chip design problems. The engineer will build LLM-powered engineering assistants and multi-turn dialogue systems, develop AI solutions for RTL linting and optimization, bug triage, formal proof convergence, and verification-report analysis, and integrate them with existing CAD/EDA flows. The role also involves maintaining design databases and dashboards that combine agentic and deterministic retrieval, and collaborating with RTL design, DV, formal verification, and CAD/EDA teams to identify needs and build AI-assisted tools.
Requirements
- Bachelor's or master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.
- 4–10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies.
- Proficiency in Python for rapid prototyping and strong fundamentals in data structures, algorithms, and software engineering practices.
- Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases.
- Strong analytical, communication, and interpersonal skills, with the ability to work effectively in a fast-paced, cross-functional startup environment.
- Proactive, self-directed approach to problem-solving and comfort operating with ambiguity.
Nice To Haves
- Familiarity with RTL design languages such as Verilog/SystemVerilog and formal/static verification tools such as JasperGold or VC Formal.
- Direct experience applying AI/ML techniques to EDA or CAD flow problems.
- Proficiency in modern software engineering practices, including version control, testing, and CI/CD.
- Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools.
- Track record of learning across AI/ML and hardware design and combining them into novel engineering solutions.
Responsibilities
- Design, develop, and deploy AI applications using LLMs, agentic frameworks, and related technologies for RTL, physical and analog design, static/lint checking, and formal verification flows.
- Build infrastructure for LLM-powered engineering assistants and multi-turn dialogue systems to help designers and verification engineers debug faster and close coverage sooner.
- Develop agentic AI solutions for RTL rule and lint checking, RTL optimization, bug triage, formal proof convergence, and static verification report analysis.
- Fine-tune and integrate AI solutions with existing CAD/EDA flows.
- Build and maintain design databases and dashboards combining agentic and deterministic retrieval to surface relevant engineering data and speed up design closure.
- Collaborate with RTL design, DV, formal verification, and CAD/EDA teams to understand pain points and translate them into AI-assisted tooling.
Benefits
- May be eligible for discretionary bonus, incentives, and benefits.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
