Senior Silicon Validation Engineer

Cynet Systems•San Jose, CA

About The Position

The Senior Silicon Validation Engineer will join a highly technical team that develops test plans, performs functional and electrical validation, and debugs issues involving new processor silicon interface features, with a strong focus on power management. The role includes developing and executing processor validation plans, contributing to platform design definition and review, and providing technical guidance and training to less experienced engineers and technicians.

Requirements

  • Bachelor's degree in Electrical Engineering or Computer Engineering with 8–10 years of related experience, or a Master's degree with 8+ years of directly related experience.
  • Experience and demonstrated technical expertise in developing and executing platform-level electrical and functional test plans.
  • Experience and demonstrated technical expertise debugging processor and PC platform I/O interfaces.
  • Demonstrated experience with or knowledge of using oscilloscopes, reading schematics and layout documentation, and Microsoft Windows and Office applications.
  • Strong verbal and written communication skills.
  • Ability to communicate effectively with a variety of engineering disciplines and management.

Nice To Haves

  • Advanced degree is considered a plus.
  • Platform-level electrical characterization experience with processor I/O interfaces is preferred.

Responsibilities

  • Write comprehensive electrical and functional test plans for processor interface validation.
  • Execute electrical and functional test plans for client processors using hardware and software validation tools, oscilloscopes, and logic analyzers.
  • Debug electrical and functional issues for new processors.
  • Provide detailed input into platform definition and review platform designs used for silicon validation of new processors.
  • Provide technical guidance and training to less experienced engineers and technicians in planning, testing, and debugging processor validation.
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