Sr. Silicon Design Engineer: Hardware-Software Co-Design

Advanced Micro Devices, Inc•Bellevue, WA

About The Position

The AMD AI Group is seeking a Senior Silicon Design Engineer to co-design the hardware-software interface for AMD Instinct GPUs. The role works with hardware architects to model and evaluate interactions among GPU microarchitecture, AI frameworks, and the ROCm software stack, using the analysis to improve performance and energy efficiency across the AI compute stack. The engineer builds performance and power models that connect architectural choices to real workload behavior; evaluates hardware features and software API designs against AI training and inference requirements; and develops and optimizes GPU kernels and compiler passes. The role spans Linux GPU compute infrastructure, the ROCm runtime, the IREE compiler, and frameworks and domain-specific languages such as PyTorch and Triton. It also contributes to open-source ROCm, performance regression infrastructure, and next-generation Instinct GPU design feedback. The position is located in San Jose, California, and is not eligible for visa sponsorship.

Requirements

Excellent communication and presentation skills, demonstrated through activities such as technical publications, presentations, trainings, or executive briefings.
Ability to collaborate effectively with engineers and other technical contributors and help elevate team knowledge and skills.
Strong computer architecture foundation, including memory consistency and coherence models, GPU microarchitecture, and pipelining.
Ability to reason precisely about hardware behavior for a given workload.
Demonstrated performance modeling skills, including building analytical or simulation-based models that predict real hardware behavior and using them to make engineering decisions.
Proficiency in C and C++ in system-level contexts and Python for tooling, analysis, and framework-level work.
Experience programming GPUs with CUDA and/or HIP, including writing and optimizing compute kernels beyond library calls.
Familiarity with Linux kernel internals relevant to GPU compute, including DRM/GEM, kernel-mode driver interfaces, memory management, and userspace-kernel interaction patterns.
Experience with compute runtimes and the full dispatch path from framework-level operations to GPU execution.
Experience with AI framework internals, such as the PyTorch dispatcher or Triton compiler, or equivalent understanding of how frameworks lower operations to hardware.
Familiarity with modern AI model architectures, such as quantization, KV cache, attention, mixture-of-experts routing, or state space models, and their hardware requirements.
Experience with GPU performance analysis tools such as profilers, trace viewers, and hardware counters, and with building custom tooling.
Bachelor’s or master’s degree in Computer Science, Computer Engineering, or a related field (listed as a preferred academic credential).

Nice To Haves

Industry experience working at the boundary of GPU compute hardware and AI systems software.
Direct experience with AMD Instinct GPU architectures such as MI300X, MI350X, or MI355X and the ROCm stack.
Working knowledge of LLVM/MLIR-based compiler flows, backend code generation, or related optimization passes.
Experience with IREE is a strong plus.
Publications or patents in HPC, ML systems, or GPU kernel optimization.

Responsibilities

Build performance and power models that relate architectural decisions to real workload behavior.
Evaluate proposed hardware features and software API designs against AI training and inference targets.
Write and optimize GPU kernels and compiler passes that use GPU microarchitectural characteristics.
Analyze AI training and inference workloads on AMD Instinct microarchitecture to identify bottlenecks, inform silicon roadmap decisions, and validate expected real-world speedups.
Collaborate with GPU hardware and firmware teams to assess how changes to memory subsystems, cache coherence protocols, and execution units affect workloads.
Develop the methodology, tooling, and benchmarks for a rapid, evidence-driven feedback loop between workload characterization and hardware design across Instinct generations.
Contribute to the IREE compiler and ROCm stack, including backend optimizations, runtime API extensions, and firmware command packet design.
Design and optimize compute runtime paths, including AI framework dispatch, data movement, and pipelining, to reduce overhead and improve hardware utilization.
Work on Linux kernel GPU compute infrastructure to improve asynchronous execution and reduce latency.
Contribute across the open ROCm ecosystem to improve the AMD AI developer experience.
Develop reproducible benchmarks and performance regression infrastructure across compiler, runtime, and driver changes.
Represent software considerations in silicon architecture reviews and communicate hardware constraints to software and framework teams.
Collaborate with AMD architecture teams to provide software feedback on next-generation Instinct GPU designs for training and inference workloads.