Senior RTL Digital Design Engineer (TERADYNE, North Reading, MA)

Teradyne•North Reading, MA

1d•$192,300 - $307,600•Onsite

About The Position

Teradyne's Digital ASIC Group is seeking a Senior RTL Digital Design Engineer to help develop complex mixed-signal ASICs for next-generation semiconductor test systems. Working closely with architects, analog designers, verification engineers, and physical design teams, you will drive digital design activities from architecture definition through silicon bring-up. This role offers the opportunity to own critical ASIC subsystems, influence technical direction, and contribute to cutting-edge products in a highly collaborative environment. The Silicon Technology Engineering (STE) organization designs high-performance ASICs that power industry-leading semiconductor test systems used by the world's leading chip manufacturers. We foster a culture of innovation, collaboration, and continuous learning where engineers solve complex technical challenges that directly influence the future of technology.

Requirements

BSEE required; MSEE or PhD desired.
8+ years of ASIC or digital design experience with strong expertise in Verilog/SystemVerilog RTL development.
Proven experience designing complex digital blocks including state machines, FIFOs, high-speed datapaths, arbitration logic, and DFT-friendly architectures.
Strong knowledge of ASIC development flows including synthesis, static timing analysis (STA), clock domain crossing (CDC), and timing closure.
Experience integrating third-party and custom IP into large-scale SoCs or mixed-signal ASICs.
Proficiency with scripting and automation using Python, Tcl, Make, or similar languages.
Experience supporting verification, silicon bring-up, debugging, and root-cause analysis.
Strong collaboration, communication, and problem-solving skills.

Responsibilities

Drive digital design activities from architecture definition through silicon bring-up.
Own critical ASIC subsystems.
Influence technical direction.
Contribute to cutting-edge products in a highly collaborative environment.
Support verification, silicon bring-up, debugging, and root-cause analysis.
Mentor junior engineers.
Drive technical excellence across cross-functional teams.