Senior RTL Design Engineer
About The Position
The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure. SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture.
Requirements
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 5+ years of experience in ASIC RTL design
- Solid foundation in computer architecture and digital logic design
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
- Experience making design decisions that trade off power, performance, and area
- Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- Experience with digital logic synthesis tools and static timing analysis
- Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
- Experience implementing SystemVerilog Assertions to check design intent
- Familiarity with tools and simulators for hardware performance analysis and tuning
- Familiarity with Git for managing release cycles
- Scripting skills in Python and Linux shell
Nice To Haves
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Exposure to a full ASIC development cycle through tape-out and production silicon
- Interest in or knowledge of AI workload acceleration techniques
- Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation
Responsibilities
- Design component units of the Reconfigurable Dataflow Unit (RDU) ASICs.
- Own blocks within a larger subsystem.
- Contribute sections of the microarchitecture specification.
- Write and debug RTL.
- Carry blocks through implementation, tape-out, and silicon bring-up.
- Work alongside principal engineers, architects, design verification, and physical design.
- Take on larger blocks as you build depth in our architecture.
Benefits
- Equity
- 95% premium coverage for employee medical insurance
- 77% premium coverage for dependents
- Health Savings Account (HSA) with employer contribution
- Dental insurance
- Vision insurance
- Short/Long term Disability insurance
- Basic Life insurance
- Voluntary Life insurance
- AD&D insurance
- Flexible Spending Account (FSA) options (Health Care, Limited Purpose, and Dependent Care)
- Full subscription to Headspace
- Gympass+ membership with access to physical gyms
- One Medical membership
- Counseling services with an Employee Assistance Program
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What This Job Offers
Job Type
Full-time
Career Level
Senior
