Senior Principal Design Verification Engineer

Renesas Electronics•Chandler, AZ

1h•Onsite

About The Position

Renesas is seeking an experienced verification engineer to lead verification efforts for its Automotive PMIC (Power Management Integrated Circuit) product line. The role combines mixed-signal verification expertise with leadership responsibilities, including mentoring junior engineers and driving verification strategy across product platforms. The position focuses on analog, digital, and mixed-signal verification, as well as debugging automotive power management systems. The engineer will design and architect mixed-signal verification environments, develop verification plans for automotive PMIC products, establish and optimize gate-level simulation flows, debug analog and digital design issues, and collaborate with cross-functional teams to support verification handoffs. The role also involves improving verification tools and methodologies and maintaining verification documentation, test plans, and coverage. Renesas is an embedded semiconductor solution provider with a global team of more than 21,000 engineers and problem solvers in over 30 countries. The company describes its culture as Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas offers a competitive benefits package alongside salary; further information is provided during the hiring process. Renesas is an equal opportunity and affirmative action employer. The role is not available for remote work. The position is subject to U.S. export control regulations, which may require an export license before technology is released to certain persons.

Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
12+ years of experience in mixed-signal or analog circuit verification.
Deep understanding of mixed-signal verification environment architecture and implementation.
Hands-on experience with RNM and AMS model integration.
Proficiency with RTL and behavioral simulation tools such as Spectre and Xcelium.
Strong understanding of GLS flows and ability to set up and debug GLS simulations.
Expertise debugging analog blocks such as switched-mode regulators, LDOs, bandgap circuits, and reference circuits, as well as digital RTL.
Experience with automotive PMIC or power management IC design and verification.
Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
Understanding of verification methodologies including UVM, assertions, and coverage-driven verification.
Experience interfacing with functional verification, post-silicon, and ATE test-correlation domains.
Strong problem-solving, debugging, and analytical skills.
Leadership and mentoring experience.

Responsibilities

Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS model integration for PMIC designs.
Develop and implement verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards including ISO 26262 and AEC-Q200.
Set up and optimize Gate-Level Simulation (GLS) flows, correlate results with RTL simulations, and identify and resolve discrepancies.
Lead debugging activities for analog blocks, including switched-mode regulators, LDO regulators, and mixed-signal interfaces.
Conduct RTL and gate-level simulations and analyze timing, power, and functional correctness across process, voltage, and temperature corners.
Collaborate with Design, Application Engineering, ATE, and Silicon Validation teams to ensure seamless verification handoffs.
Mentor and lead junior verification engineers, define best practices, and establish verification methodologies.
Troubleshoot complex issues involving interactions between analog and digital domains using simulation and measurement techniques.
Improve verification tools, methodologies, and infrastructure, and evaluate emerging verification technologies and AI-based solutions.
Create and maintain verification documentation, test plans, and coverage.