Senior Principal ASIC Design Engineer

Hewlett Packard Enterprise•Roseville, CA

1d•$174,000 - $352,500•Onsite

About The Position

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. HPE Networking is a leading provider of advanced routers and switches that keep the world connected with speed, reliability, security, and simplicity. Within the HPE Networking Silicon group, we push the boundaries of silicon innovation by building cutting-edge networking chips that power world-class routing and switching platforms. Bring your passion, creativity, and technical depth to a team where there are few boundaries to what you can accomplish. We operate with the agility of a start-up inside a global technology company, and year after year our team delivers some of the industry’s most powerful and highest-density networking silicon. As part of our fast-paced chip design organization, you will help define, design, and implement high-speed ASICs from product requirements and architecture through final netlist. You will work on complex, high-impact subsystems, collaborate with system design teams across geographies, and have significant opportunities to shape both product capability and engineering methodology. Our culture is built on open communication, empowerment, innovation, teamwork, and customer success. In this environment, you will have the opportunity to set ambitious goals, expand your technical leadership, and make a lasting contribution to high-performance networking products. Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication. Contributions have substantial technical impact on a significant HPE product/project, or a strategic/architectural direction. Go-to creator and innovator for critical business challenges and opportunities. Substantial, unique contributions provide long-lasting, recurring benefits like time-to-market improvements, cost reductions, or satisfying future and current unmet customer needs. Recognized internal authority on key technology areas. Provides technical leadership to the business for significant project/program work. Leads and connects others across functions to unite around a common goal. Actively mentors others and contributes to the HPE technical community.

Requirements

Bachelor’s degree in Electrical Engineering or a related field is required; a Master’s degree is preferred.
Candidates should have 15+ years of relevant ASIC design experience.
Strong analytical, problem-solving, and technical decision-making skills.
Demonstrated experience architecting and implementing high-performance ASIC subsystems from specification through final netlist.
Proven technical leadership experience, preferably as a chip lead or subsystem lead on prior ASIC development programs.
Experience in at least two of the following areas: 10G–800G Ethernet interface standards; HBM2, HBM2E, DDR4, or related memory technologies and integration; security protocols such as MACsec and IPsec; networking protocols and deep packet inspection; schedulers; queuing and memory subsystems; and fixed-function or microcode-based packet processing.
Strong coding skills in Verilog and SystemVerilog, demonstrated through prior ASIC implementation experience.
Broad understanding of ASIC architecture, including front-end design, subsystem integration, verification interfaces, timing, power, area trade-offs, and production tape-out execution.
Excellent written and verbal communication skills.

Nice To Haves

Prior first-authored patents in networking or computer architecture are a plus.
Knowledge of synthesis, lint, CDC, formal, and other advanced EDA tools used in a modern ASIC development flow is highly desired.
Familiarity with AI agents, AI skills, and automation frameworks that improve ASIC design productivity, design-space exploration, documentation quality, and review efficiency is strongly desired.
Working knowledge of Perl and Python is strongly desired.
Track record of successful tape-outs of multiple high-performance ASICs, with technical leadership responsibility for a full chip or complex subsystem.
Proven design leadership across the full ASIC lifecycle, including architecture, micro-architecture, implementation, methodology automation, and cross-functional execution across design, verification, software, physical design, and product teams.

Responsibilities

Serve as the technical lead for a significant subsystem within a high-performance networking ASIC, defining the architecture from the ground up and translating product, hardware, and software requirements into a detailed and executable subsystem specification.
Partner with product marketing, hardware, software, verification, and physical design teams to evaluate feasibility, make informed trade-offs, and deliver a design that meets power, area, performance, timing, and feature objectives.
Author clear and comprehensive functional and micro-architecture specifications for assigned modules and subsystems.
Implement complex RTL modules and subsystems using Verilog or SystemVerilog, with attention to quality, maintainability, timing closure, and design reuse.
Develop functional coverage and SystemVerilog Assertions to support verification quality and help identify corner-case bugs early in the design cycle.
Apply state-of-the-art power reduction techniques during architecture and implementation to ensure the design meets aggressive power targets.
Collaborate closely with the physical design team on floorplanning, timing closure, and RTL-level timing fixes required to achieve frequency targets.
Work with the verification team to ensure the assigned block or subsystem is fully validated against functional, performance, and integration requirements.
Provide technical leadership, guidance, and mentoring to engineers across the design team.
Drive continuous improvement of design methodologies through advanced EDA flows, automation, power optimization techniques, and disciplined design review practices.
Champion automation and AI-assisted design methodology, including practical use of AI agents, AI skills, scripts, and workflow orchestration to accelerate specification development, RTL quality checks, debug, documentation, and design closure.
Lead architecture-level trade-off discussions across major ASIC subsystems, ensuring that feature definition, performance, power, area, timing, verification, software, and physical design considerations are balanced from concept through tape-out.