Senior Physical Design Engineer for Core IP

Intel CorporationHillsboro, OR
$164,470 - $269,100Onsite

About The Position

As a member of the CPU development team, you will have a front seat in designing the latest core IP to power cutting-edge compute processors across client, server, IOTG, and AI. We innovate state-of-the-art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap.

Requirements

  • Bachelors in Computer/Electrical Engineering or related field with 10+ years of relevant work experience. Or a Masters in the same field with 5 + years of relevant work experience.
  • 10+ years of experience in integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
  • PV convergence (including static timing and power analysis)
  • Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
  • Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
  • Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Nice To Haves

  • Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • Static Timing Analysis, Noise analysis, and reliability verification techniques
  • RTL to GDS methodologies and formal equivalence
  • Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

Responsibilities

  • Synthesis and Place and Route using industry standard tools for high speed CPU core design
  • Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure
  • Develop strategies to deliver reproducible design convergence results
  • Help to create and refine synthesis flow for the project team
  • Develop and recommend better design method practices to enable better synthesis convergence
  • Perform CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements
  • Generate and verify timing constraints while addressing timing violations at the chip or block level for CPU cores
  • Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning

Benefits

  • competitive pay
  • stock bonuses
  • health
  • retirement
  • vacation
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