Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Laboratory•Laurel, MD

19h•Onsite

About The Position

The Miniature Device Technologies Group develops highly customized tools and techniques required to carry out missions around the globe. Whether it be a quick reaction need from the field or the long-term development of a novel capability, we work hand in hand with our government sponsors to conceive and realize solutions to their most challenging problems. We leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives. We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature systems for a wide range of applications. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks. You will be working closely with the ASIC design team to identify back-end issues, and assist in addressing these issues, both in the RTL and gate-level phases of the design. You will help explore process selection for new proposals and designs, assessing aspects such as achievable size and power, and availability of the necessary design features and intellectual property (IP.) Additionally, you will perform custom physical design as needed, both to complete custom block layouts, and to perform custom modifications necessary at the top level of the ASIC.

Requirements

Associate’s degree in a technical field, or a combination of equivalent level experience/education/certifications.
Skilled at using Cadence ASIC design tools for back-end flow implementation
Skilled at using Siemens Calibre physical verification tools
6+ years of experience specifically performing back-end ASIC design
Able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance.
U.S. citizenship

Nice To Haves

Experience with custom physical layout in Cadence Virtuoso
Skilled at using Siemens ASIC design tools for back-end flow implementation
Extensive knowledge and experience in ASIC technology characterization for process selection
Hold an active clearance and/or have successfully undergone single-scope background investigations in the past.

Responsibilities

Digital back-end flow, from synthesis to a completed, verified top-level layout, ready for tapeout submission
Contribute to process selection for new designs and proposals
Floorplan the top-level layout of the digital and mixed-signal ASICs
Perform timing analysis and design partitioning
Perform SCAN and BIST insertion for maximum defect coverage
Work with digital designers to debug and address back-end related RTL and gate-level issues
Perform all physical verification, including DRC, DRC+, MCD, and LVS
Perform custom physical layout
Assist with ASIC design environment enhancements and scripting
Demonstrate initiative by identifying and driving process improvements, and implementing innovative solutions to complex design challenges
Build and maintain strong working relationships with cross-functional teams, including digital design, verification, and software teams
Provide leadership and guidance to junior physical design engineers, and contribute to their growth and development
Collaborate with the team to achieve project goals and objectives, and drive results through effective teamwork and problem-solving
Foster open communication and collaboration with digital designers, junior physical design engineers, and other stakeholders to ensure seamless project execution