Senior Engineer, Physical Design Engineering (ASIC)

Analog Devices•Wilmington, MA

6d•$116,960 - $160,820•Onsite

About The Position

As a Senior Physical Design Engineer, you will play a key role in the implementation and delivery of complex digital and mixed-signal IC designs. You will work across the physical design flow, from floorplanning through place-and-route, timing closure, physical verification, and tapeout support, helping turn architectural and RTL intent into robust silicon implementation. This role requires strong technical depth in physical design, the ability to solve complex implementation challenges, and effective collaboration with cross-functional teams across the development cycle.

Requirements

Strong experience in physical design for ASIC/SoC development, including successful implementation through tapeout
Expertise in floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verification
Strong understanding of timing analysis, constraints, signal integrity, power optimization, and physical design trade-offs
Experience with industry-standard physical design and signoff tools, including Cadence-based flows
Scripting experience in TCL, Python, or similar languages for automation and flow improvement
Experience collaborating across cross-functional teams including RTL, STA, DFT, design verification, and package or product engineering
Strong problem-solving and debug skills across backend implementation challenges
Clear communication and technical documentation skills
Demonstrated ability to independently drive complex blocks or major implementation workstreams

Nice To Haves

Experience with advanced-node implementation and low-power design methodologies
Familiarity with mixed-signal integration considerations and top-level implementation challenges
Experience improving backend flows, automation, or methodology
Prior mentoring experience or informal technical leadership on project execution

Responsibilities

Own physical design implementation for complex digital blocks and subsystems, including floorplanning, placement, clock tree synthesis, routing, and physical optimization
Drive timing closure, congestion analysis, power optimization, and area improvement across assigned blocks or subsystems
Perform physical verification activities including DRC, LVS, ERC, and reliability checks in collaboration with relevant teams
Develop and refine physical design constraints, scripts, and flow improvements to improve quality and execution efficiency
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve design and implementation issues
Support block-level and top-level integration activities, including interface planning, timing constraint alignment, and implementation readiness
Analyze and debug timing, signal integrity, power, and physical implementation issues across the full backend flow
Contribute to methodology improvements and help establish best practices for physical design execution
Participate in design reviews and provide clear technical input on implementation trade-offs, risks, and readiness
Author and maintain documentation for design implementation, constraints, flows, and signoff status
Mentor junior engineers on physical design practices, tool usage, and debugging approaches
Support tapeout planning and execution activities to ensure high-quality delivery against project milestones