IP Validation Design Engineer

Advanced Micro Devices, Inc•Vancouver, BC

7h•Hybrid

About The Position

The AMD NBIO Team is on the lookout for a dynamic, upbeat IP Validation Design Engineer to join our growing team. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. You have a passion for modern, complex processor architecture, digital design, and validation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You are a self-starter with strong analytical and problem-solving skills and are willing to learn and ready to independently drive tasks to completion.

Requirements

Experience in digital logic design/verification/post-silicon validation.
Extensive experience with ASIC debug techniques and methodologies.
Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization.
Strong scripting skills (eg. Ruby, Python).
Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
Must have excellent written and verbal communication skills.
Must excel in a dynamic team working environment.
Must be a self-starter and be able to independently drive tasks to completion.
Bachelor’s or master’s degree majoring in EE, CS or related field

Nice To Haves

Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK is an asset
In-depth knowledge of PC architectures/PCIe protocol is an asset.
Leadership and mentoring skills a definite asset.

Responsibilities

Drive the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs.
Define, document, execute and report the overall functional test plan and validation strategy for a set of AMD IP’s.
Drive technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
Debug IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs.
Engage on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.
Lead collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.
Develop knowledge of system architecture/debug and other internal IP’s.
Support issues on customer platforms as requested by customer support teams.