IP Design Verification Engineer

Intel Corporation•Santa Clara, CA

6d•$91,150 - $172,860•Hybrid

About The Position

As an IP Design Verification Engineer, you will play a pivotal role in ensuring the functionality, quality, and reliability of cutting-edge IP designs that power industry-leading products. By joining our team, you will directly contribute to Intel's mission of advancing technology to enrich lives worldwide. You will have the opportunity to work closely with a multidisciplinary team of architects, RTL developers, and physical design engineers to deliver high-quality verification solutions and solve complex technical challenges. This role is an excellent starting point for building a meaningful career in design verification, with opportunities for growth, learning, and innovation in a collaborative environment.

Requirements

Bachelor’s in electrical engineering or computer engineering or computer science, or a related technical engineering field.
1+ years of experience in IP design verification or a related domain.
Must have the anticipated degree or expect to have the anticipated degree by July 2026.
6+ months of experience with the following technical skills: Proficiency in debugging techniques and tools to identify and resolve issues.
Knowledge of RTL design concepts and methodologies.
Familiarity with design for verification (DFV) principles and practices.
Understanding of developing and maintaining IP test environments.

Nice To Haves

Master's degree in a relevant field.
Familiarity with scripting languages (e.g., Python or Perl) to automate workflows.
Strong communication and team collaboration skills, with the ability to work effectively in a cross-functional environment.
A passion for innovation, continuous learning, and problem-solving in a technical domain.

Responsibilities

Develop functional verification plans and test benches based on microarchitecture specifications.
Design and maintain verification environments that ensure comprehensive coverage and robust testing of IP logic.
Execute verification plans and perform system simulations to confirm compliance with specifications, analyze power and timing, and identify bugs.
Debug issues in the pre silicon environment, identify root causes, and implement corrective measures to address failing tests.
Collaborate with architects, RTL designers, and physical design teams to verify complex architectural and microarchitectural features.
Document test plans, participate in technical reviews, and drive improvements to verification strategies and infrastructure.
Maintain and enhance existing functional verification methodologies and frameworks.
Contribute to the definition and optimization of new verification infrastructure and related tools and flows.