Design Verification Engineer
About The Position
AMD’s Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD’s data center product portfolio with a high‑performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle. We are seeking a high‑impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high‑performance ASIC designs. The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels. You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking products.
Requirements
- Expert‑level knowledge of SystemVerilog and UVM
- Strong hands‑on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
- Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies
- Strong debug skills across architecture, RTL, and testbench layers
- Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑path components
- Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure
- Bachelor’s Degree in Electrical/Computer Engineering or related field
Nice To Haves
- Experience with performance verification, power‑aware verification (UPF), or formal verification
- Familiarity with FPGA/HAPS‑based validation and acceleration flows
- Understanding of networking or high‑speed I/O pipelines
- Exposure to architectural modeling or C/C++ reference models
- Strong analytical and problem‑solving abilities with a proven track record of debugging complex issues
- Ability to lead verification tasks independently and drive cross‑team closure
- Excellent verbal and written communication skills
- Comfortable working in a fast‑paced, collaborative, multi‑site environment
- Ability to mentor and guide junior DV engineers
- Master’s Degree Preferred
Responsibilities
- Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
- Drive test plan creation, feature mapping, and coverage strategy for complex networking and data‑path IP.
- Develop high‑quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
- Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
- Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
- Optimize simulations, coverage closure, and verification sign‑off methodology.
- Use industry‑standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
- Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).
- Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high‑quality deliverables.
- Participate in design reviews, micro‑architecture definition, and bring a verification perspective into early design stages.
- Mentor junior engineers and provide technical leadership within the verification team.
Benefits
- AMD benefits at a glance
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What This Job Offers
Job Type
Full-time
Career Level
Senior
