Design Verification Engineer

Arrow•Denver, CO

1d•Hybrid

About The Position

eInfochips Inc. is seeking a Design Verification Engineer to develop strategies for verification by understanding design architecture and design specifications. The role involves capturing all requirements/features of the design to create functional verification plans, including Test Plan, Checker Plan, Coverage Plan, and Data Checkers. The engineer will develop a self-checking verification test bench for a data center product using System Verilog and a UVM-based customized methodology, including developing random/directed testing scenarios to achieve coverage goals and developing parameterized Verification components. Integration of reusable verification components and bringing up an integrated verification environment are also key responsibilities. The role includes developing functional coverage, firmware, and test scenarios for the processor, as well as SVA development. Functional verification and simulation of scenarios, including regression runs and analysis, will be shared with the Design team. Development of complex corner case scenarios for bulk/stress verification of the design and debugging of complex verification environments, test benches, and RTL issues are critical. Thorough analysis of Functional and Code coverage to achieve 100% closure is required.

Requirements

Bachelor’s degree or foreign equivalent in Electronics and Communication Engineering or related field and 8 years of progressively responsible post-baccalaureate work experience in the Design Verification Engineer position, job offered, or related occupation.
System-level verification, digital design, and ASIC design
Hardware description languages
UVM testbench development: creation and integration of UVM components, agents, drivers, monitors, and scoreboards
AXI performance verification: measuring throughput, latency, and bandwidth utilization under diverse traffic scenarios, and conducting stress testing to ensure interconnect reliability
CPU verification methodologies, including functional and performance validation of processor pipelines, cache coherence, and memory management.

Responsibilities

Develop strategies for verification by understanding design architecture and design specifications.
Capture all requirements/features of design to create functional verification plans for its thorough verification, including Test Plan, Checker Plan, Coverage Plan, Data Checkers.
Develop self-checking verification test bench for chip using System Verilog and UVM based customized methodology for data center product, including developing random/directed testing scenarios to achieve coverage goals and developing parameterized Verification component.
Integrate earlier developed re-usable verification components into current verification testbench and bring up integrated verification environment.
Develop functional coverage.
Develop firmware and test scenarios for the processor.
SVA (System Verilog Assertion) development.
Functional Verification and simulation of scenarios including regression run and its analysis, also share them to the Design team.
Complex corner case scenarios development for bulk/stress verification of design.
Debugging of complex verification environment, test bench and RTL issues.
Thorough analysis of Functional and Code coverage.
Achieve Functional and Code Coverage closure to 100%.