IP Design Intern

Altera•Toronto, ON

2d•CA$85,000 - CA$95,000•Onsite

About The Position

Join Altera IP solutions team and work on cutting edge FPGA RTL and IP design! Altera's IP Solutions Engineering (IPSE) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera’s FPGA devices. These solutions are provided as highly configurable intellectual property (IP) cores that are fully integrated with Altera's software CAD tool, Quartus Prime. The External Memory Interfaces (EMIF) team is responsible for developing IPs for communication with state-of-the-art DDR and LPDDR devices. The ever-growing demand for faster and higher-density memories - especially in the data center and machine learning sectors - presents a challenging design problem that requires system-level knowledge of silicon, software, IP, and customer applications. You will work with a team of engineers to develop and verify state-of-the-art External Memory IP cores for interfacing with DDR5 and LPDDR5 memories. You will be working on advanced FPGA architectures, design definition, implementation, and verification. Additionally, you will also be developing design examples and simulation models, accompanied by a rich set of technical documentation. In this role, you will work closely with multiple teams, including silicon design and validation, post-silicon validation, application engineering, and customer experience teams, to ensure seamless development, integration, and optimization of high-speed interface IP solutions.

Requirements

Currently pursuing a BS degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or related field
3+ months of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification
3+ months of experience in scripting languages and/or software programming (e.g. Python/TCL/Perl and/or C/C++)

Nice To Haves

FPGA design experience
Experience with RTL simulation, timing closure and static timing analysis
Experience with DDR and/or LPDDR hardware interfaces

Responsibilities

Architecture and Design based on the latest protocol specifications for DDR and LPDDR devices
RTL development
Device support and CAD tool integration
Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)
Hardware power-on and debug
New product release and rollout support
Customer technical support