Senior OPC R&D Engineer

Solidigm•San Jose, CA

3d•$159,360 - $255,000•Hybrid

About The Position

As a lead Optical Proximity Correction (OPC) R&D Engineer, develop and implement high-quality technology solutions to optimize pattern fidelity, process window, and reliability for critical memory patterning layers. Use industry-standard software to model and correct optical and other patterning effects, and apply design for manufacturability (DFM) and resolution enhancement techniques (RET) so final chip layouts transfer accurately to wafers and meet manufacturing requirements. Guide other engineers in developing these solutions. The role includes developing OPC models and recipes, leading patterning development and tapeout readiness, evaluating OPC performance with wafer data and simulations, and providing technical guidance and training to internal teams. Collaborate with design rule, lithography, process integration, tapeout, mask engineering, and development fab teams. The position is primarily office-based, is hybrid, and can be aligned to San Jose or Rancho Cordova, California. Some international travel is expected. Relocation is available.

Requirements

Master’s or PhD in a related science or engineering discipline, such as Physics, Materials Science, Electrical Engineering, or Chemical Engineering.
At least 5 years of proven technology development experience in semiconductor patterning technical areas.
Strong understanding of patterning technologies and concerns, including optical proximity effects, RET such as SMO, and DFM methodologies.
Proficiency with industry-standard OPC and SMO software, such as Mentor, Synopsys, or ASML Brion.
Proficiency in scripting languages such as Python, TCL, or Perl; C++ may also be used.
Ability to analyze large datasets, perform statistical analysis, and interpret simulation results.
Problem-solving and analytical skills to address complex technical problems related to RET/OPC, tapeout, design rules, and semiconductor patterning processes.
Communication and teamwork skills to communicate technical information and collaborate across design, technology development, and manufacturing teams.

Nice To Haves

At least 7 years of experience in OPC/RET or related areas delivering high-quality patterning solutions.
Strong understanding of semiconductor manufacturing technologies and the overall chip fabrication process, especially NAND flash manufacturing.

Responsibilities

Drive development, implementation, and optimization of OPC models and recipes, including advanced DFM and RET techniques for critical memory layers.
Lead patterning development through SMO studies, test plate design, and design rule evaluations.
Validate OPC solution tapeout readiness and conduct quality reviews with lithography and process integration teams.
Lead the patterning team in resolving hotspot issues using data-driven solutions.
Work with development fab engineers to ensure the quality and performance of OPC solutions.
Use validation and simulation software tools to guide wafer data collection for OPC verification and optimize mask quality, pattern fidelity, and process window.
Create documentation and training to help internal teams understand and use OPC tools and methodologies.
Provide technical support and guidance to internal teams using OPC tools, helping resolve issues and optimize designs or processes.
Collaborate with design rule, lithography, process integration, tapeout, and mask engineering teams to align OPC with the overall chip manufacturing process.