Senior OPC R&D Engineer
About The Position
As a lead Optical Proximity Correction (OPC) R&D Engineer, develop and implement high-quality technology solutions—and guide other engineers in doing so—to optimize pattern fidelity, process window, and reliability for critical memory patterning layers. Use industry-standard software to model and correct optical and other patterning effects, and apply design-for-manufacturing (DFM) and resolution enhancement technology (RET) solutions so that chip layouts transfer accurately to wafers and meet manufacturing requirements. The role is hybrid and can be aligned to San Jose or Rancho Cordova, California, with relocation available. It is primarily office-based and involves some international travel.
Requirements
- Master's or Ph.D. in a related science or engineering discipline, such as physics, materials science, electrical engineering, or chemical engineering.
- At least 5 years of proven technology-development experience in semiconductor patterning technical areas.
- Strong understanding of patterning technologies and concerns, including optical proximity effects, RET such as SMO, and DFM methodologies.
- Proficiency with OPC and SMO software, including industry-standard tools such as Mentor, Synopsys, or ASML Brion.
- Proficiency in scripting languages such as Python, TCL, or Perl; C++ may also be used.
- Ability to analyze large datasets, perform statistical analysis, and interpret simulation results.
- Problem-solving and analytical skills to address complex technical issues related to RET/OPC, tapeout, design rules, and semiconductor patterning processes.
- Ability to communicate technical information effectively and collaborate across design, technology development, and manufacturing teams.
Nice To Haves
- 7 or more years of experience in OPC/RET or related areas delivering high-quality patterning solutions.
- Strong understanding of semiconductor manufacturing technologies and the overall chip fabrication process, especially NAND flash manufacturing.
Responsibilities
- Drive the development, implementation, and optimization of OPC models and recipes, including advanced DFM and RET techniques, for critical memory layers.
- Lead patterning development through source mask optimization (SMO) studies, test plate design, and design rule evaluations.
- Validate OPC solution tapeout readiness and conduct quality reviews with lithography and process integration teams.
- Lead the patterning team in resolving hotspot issues quickly using data-driven solutions.
- Work with development fab engineers to ensure OPC solution quality and performance.
- Use validation and simulation software to guide wafer data collection for OPC verification and optimize mask quality, pattern fidelity, and process window.
- Create and own documentation and training to help internal teams understand and use OPC tools and methodologies.
- Provide technical support and guidance to internal users of OPC tools, helping them resolve issues and optimize designs or processes.
- Collaborate with design rule, lithography, process integration, tapeout, and mask engineering teams to align OPC processes with overall chip manufacturing.
Benefits
- Medical, dental, and vision insurance.
- Supplemental life and AD&D insurance.
- Short- and long-term disability coverage.
- Healthcare and dependent care flexible spending accounts.
- Company match on eligible 401(k) plan contributions.
- Eligibility to participate in restricted stock unit (RSU), restricted cash unit (RCU), and cash bonus programs.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
