OPC Technology Transfer Engineer (R&D)

Texas Instruments•Dallas, TX

About The Position

As a Senior OPC Technology Transfer Engineer within Texas Instruments’ Advanced Technology Development organization, you will bridge initial R&D development and high-volume manufacturing (HVM) by owning the lifecycle of transferring developed OPC technologies to production Fabs. You will analyze process, equipment, layout, and tool differences between R&D and HVM environments to identify, mitigate, and resolve transfer risks before recipe release, supporting a seamless, high-yield production ramp-up. The role applies semiconductor process expertise, particularly in photolithography and etching, to align transferred OPC solutions with production-line physics and hardware. You will work across organizational boundaries with manufacturing operators, shift technicians, and Fab staff to coordinate test wafer execution and align expectations. You will also use data science methods to analyze wafer measurement datasets and assess OPC recipe performance for manufacturing sign-off; compile and analyze SEM images and Critical Dimension (CD) data to compare R&D software models with production silicon; and review automated OPC verification results to identify critical lithographic care-abouts and select metrology targets for layout review and CD-SEM tracking.

Requirements

Master’s degree in Electrical Engineering, Physics, Computer Science, Chemistry, or a related field.
At least 5 years of experience in semiconductor photolithography and/or OPC development.
Lithography and RET expertise for 45nm, 28nm, 22nm, or 20nm processing nodes.
Hands-on experience handling high-volume SEM measurement data and image inspections.
Strong layout review skills using OPC verification tools to determine and isolate critical metrology targets.
Profound understanding of OPC development flows, process-window optimization, and design-rule constraints.

Nice To Haves

Strong knowledge of advanced lithography processes, lithography simulation techniques, mask making, and RET techniques used in semiconductor manufacturing and process development.
Demonstrated leadership and ability to influence cross-functional teams and communicate technical requirements effectively to manufacturing staff on the Fab floor.
Familiarity with physical layout formats (GDS/OAS), lithography/OPC test-pattern design, test-pattern generators, and layout software such as Virtuoso or KLayout.
Programming experience in a Unix environment.
Understanding of OPC pattern-validation methodologies and process-window assessment techniques such as KLA’s Photolithography Wafer Qualification (PWQ).
Strong analytical and problem-solving skills.
Strong verbal and written communication skills.
Ability to collaborate effectively with people in different functions.
Strong time-management skills and ability to deliver projects on time.
Demonstrated ability to build strong, influential relationships.
Ability to work effectively in a fast-paced, rapidly changing environment.
Ability to take initiative and drive results.

Responsibilities

Own the lifecycle of transferring developed OPC technologies from R&D to production Fabs.
Analyze process, equipment, layout, and tool differences between R&D and HVM environments to identify, mitigate, and resolve transfer risks before recipe release.
Align transferred OPC solutions with production-line physics and hardware characteristics, using expertise in photolithography and etching.
Coordinate test wafer execution with manufacturing operators, shift technicians, and Fab staff, aligning expectations and collaboration.
Collect, analyze, and interpret large-scale wafer measurement datasets to assess OPC recipe performance for manufacturing sign-off.
Compile and analyze high-volume SEM images and Critical Dimension data to verify R&D software model behavior against production silicon.
Analyze automated OPC verification results to identify lithographic critical care-abouts and select metrology targets for layout review and CD-SEM measurement tracking.