OPC Technology Transfer Engineer (R&D)

Texas Instruments•Dallas, TX

About The Position

As a Senior OPC Technology Transfer Engineer within the Advanced Technology Development (ATD) organization, you will bridge initial R&D development and high-volume manufacturing (HVM) by owning the full lifecycle of transferring developed OPC technologies to production fabs. You will analyze process, equipment, layout, and tool differences between R&D and HVM environments to anticipate, mitigate, and resolve transfer risks before recipe release, supporting a seamless, high-yield production ramp-up. The role applies technical knowledge of semiconductor photolithography and etching to align transferred OPC solutions with production-line physics and hardware characteristics. You will work across organizational boundaries with manufacturing operators, shift technicians, and fab staff to coordinate test-wafer execution and align expectations. You will use data-science methods to collect, analyze, and interpret large wafer-measurement datasets to evaluate OPC recipe performance for manufacturing sign-off. You will also analyze SEM images and critical-dimension (CD) data to verify R&D software-model behavior against production silicon. In addition, you will review automated OPC verification results to identify lithographic critical care-abouts and select metrology targets for layout review and CD-SEM tracking.

Requirements

  • Master’s degree in Electrical Engineering, Physics, Computer Science, Chemistry, or a related field.
  • At least 5 years of experience in semiconductor photolithography and/or OPC development.
  • Lithography and RET expertise for 45 nm, 28 nm, 22 nm, or 20 nm processing nodes.
  • Hands-on experience handling high-volume SEM measurement data and image inspections.
  • Strong layout-review skills using OPC verification tools to determine and isolate critical metrology targets.
  • Profound understanding of OPC development flows, process-window optimization, and design-rule constraints.

Nice To Haves

  • Strong knowledge of advanced lithography processes, lithography simulation techniques, mask making, and RET techniques used in semiconductor manufacturing and process development.
  • Demonstrated leadership and ability to influence cross-functional teams and communicate technical requirements effectively to manufacturing staff on the fab floor.
  • Familiarity with physical layouts (GDS/OAS).
  • Knowledge of lithography/OPC test-pattern design and layout execution using test-pattern generators, and experience with layout software such as Virtuoso or KLayout.
  • Programming experience in a Unix environment.
  • Understanding of OPC pattern-validation methodologies and process-window assessment techniques such as KLA’s Photolithography Wafer Qualification (PWQ).
  • Strong analytical and problem-solving skills.
  • Strong verbal and written communication skills.
  • Ability to work in teams and collaborate effectively with people in different functions.
  • Strong time-management skills that enable on-time project delivery.
  • Demonstrated ability to build strong, influential relationships.
  • Ability to work effectively in a fast-paced and rapidly changing environment.
  • Ability to take initiative and drive for results.

Responsibilities

  • Own the lifecycle of transferring developed OPC technologies from R&D to production fabs.
  • Analyze process, equipment, layout, and tool differences between R&D and HVM environments to identify and address transfer risks before recipe release.
  • Align transferred OPC solutions with production-line physics and hardware characteristics, drawing on photolithography and etching knowledge.
  • Partner with manufacturing operators, shift technicians, and fab staff to coordinate test-wafer execution and align expectations.
  • Collect, analyze, and interpret large-scale wafer-measurement datasets to evaluate OPC recipe performance for manufacturing sign-off.
  • Compile and analyze high-volume SEM images and critical-dimension (CD) data to verify R&D software-model behavior against production silicon.
  • Analyze automated OPC verification results to identify lithographic critical care-abouts and select metrology targets for systematic layout review and CD-SEM measurement tracking.
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