Senior Manager- SOC Verification

Microchip • Chandler, AZ

1d

About The Position

As the SoC Verification Manager, you will lead verification for next-generation 32-bit MCU products in Microchip Technology’s dsPIC Microcontroller Business Unit. You will lead, mentor, and scale a global team of more than 20 verification engineers and drive first-pass silicon success by connecting architectural intent with silicon implementation through UVM and formal verification methodologies.

The role owns verification strategy from initial test-plan development through final tape-out sign-off across multiple concurrent MCU projects. It oversees reusable testbench architecture for simulation-based and formal verification, advances verification techniques and automation, and collaborates with Architecture, RTL Design, DSP, and Physical Design teams to resolve integration issues and architectural bottlenecks. The position also focuses on improving verification efficiency through scripting and AI-driven tools.

Requirements

• Bachelor of Science in Electrical Engineering or Computer Science, with strong digital design fundamentals.
• At least 15 years of SoC Verification experience.
• At least 5 years in a formal leadership or management role.
• Proven track record of successful tape-outs for 32-bit microcontrollers.
• Deep understanding of MCU peripherals, including DMA, timers, ADC/DAC interfaces, and security modules.
• Direct experience verifying SoCs with ARM Cortex-M cores and proprietary RISC-based architectures.
• Expert-level command of SystemVerilog and UVM (Universal Verification Methodology).
• Strong hands-on experience with Formal Verification, including property checking and connectivity checking, using tools such as JasperGold or VC Formal.
• In-depth knowledge of AMBA bus protocols, including AHB, APB, and AXI.
• Experience defining coverage-driven verification (CDV) metrics and managing large regression suites.

Nice To Haves

• Strong background in Gate-Level Simulations (GLS) and power-aware verification.
• Experience with Post-Silicon Validation and customer support, and aligning these with pre-silicon test plans.
• Experience with analog mixed-mode (AMS) simulations.
• Familiarity with functional safety standards (ISO 26262) for automotive MCU applications.

Responsibilities

• Own end-to-end verification strategy, from initial test-plan development to final tape-out sign-off for multiple concurrent MCU projects.
• Lead and develop a global team of more than 20 engineers, including resource allocation, performance reviews, and technical career growth.
• Define and refine scalable, reusable testbench architectures supporting UVM simulation and formal verification flows.
• Drive adoption of Formal Verification, Power-Aware Verification (UPF/CPF), and Hardware-Software Co-verification.
• Partner with Architecture, RTL Design, Digital Signal Processing (DSP), and Physical Design teams to resolve integration issues and architectural bottlenecks.
• Improve verification efficiency through automation, Python/Perl scripting, and integration of AI-driven verification tools.
• Develop module-level verification plans and testbench plans; develop testbenches and integrate module-level testbenches at full-chip level.
• Develop functional assertions and coverpoints.
• Define coverage-driven verification metrics and manage regression suites.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior