Senior Manager- SOC Verification

Microchip Technology Inc.•Chandler, AZ

2d•Onsite

About The Position

Microchip Technology Inc. is seeking a Senior Manager for SoC Verification within its dsPIC Microcontroller Business Unit. This role is crucial for ensuring the functional integrity of next-generation 32-bit MCU products. The successful candidate will lead, mentor, and scale a team of over 20 verification engineers, executing complex verification strategies for SoCs that include ARM and specialized proprietary cores. The primary mission is to achieve "First-Pass Silicon Success" by effectively bridging architectural intent and silicon implementation using advanced UVM and Formal methodologies.

Requirements

Bachelor of Science in Electrical Engineering or Computer Science, with strong digital design fundamentals.
15+ years in SoC Verification, with at least 5 years in a formal leadership or management role.
Proven track record of successful tape-outs for 32-bit Microcontrollers.
Deep understanding of MCU peripherals (DMA, Timers, ADC/DAC interfaces, Security modules).
Direct experience verifying SoCs with ARM cores (Cortex-M) and proprietary RISC-based architectures.
Expert-level command of SystemVerilog and UVM (Universal Verification Methodology).
Strong hands-on experience with Formal Verification (Property Checking, Connectivity Checking) using tools like JasperGold or VC Formal.
In-depth knowledge of AMBA bus protocols (AHB, APB, AXI).
Experience defining coverage-driven verification (CDV) metrics and managing massive regression suites.
Module level verification plan development, TB plan, TB development and fullchip integration of the module level TB, develop effective functional assertions and coverpoints.

Nice To Haves

Strong background in Gate-Level Simulations (GLS) and power-aware verification.
Experience with Post-Silicon Validation, customer support and its alignment with pre-silicon test plans.
Experience with analog mixed-mode (AMS) simulations.
Familiarity with functional safety standards (ISO 26262) for automotive MCU applications.

Responsibilities

Own the end-to-end verification strategy, from initial test plan development to final tape-out sign-off for multiple concurrent MCU projects.
Lead and develop a global team of 20+ engineers, managing resource allocation, performance reviews, and technical career growth.
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows.
Drive the adoption of advanced techniques, including Formal Verification, Power-Aware Verification (UPF/CPF), and Hardware-Software Co-verification.
Partner closely with Architecture, RTL Design, Digital Signal Processing (DSP), and Physical Design teams to resolve complex integration issues and architectural bottlenecks.
Continuously improve verification efficiency through automation, Python/Perl scripting, and the integration of AI-driven verification tools.