Senior Lead Design Engineer

Altera•San Jose, CA

1d•$231,500 - $330,000•Onsite

About The Position

Altera is seeking a Senior Lead Design Engineer to provide hands-on technical leadership for the architecture, design, and delivery of next-generation FPGA and programmable SoC solutions. This senior individual-contributor and technical leadership role influences technical direction across complex subsystems, product generations, and global engineering teams. The role leads the definition and implementation of high-performance digital logic and reusable IP for programmable devices and platform solutions. It translates product and system requirements into scalable architectures, drives design decisions, and guides execution from early concept through RTL delivery, validation, and product readiness. The position supports solutions for data center, networking, AI, and edge applications. The successful candidate brings deep experience in complex ASIC, SoC, or FPGA development, a rigorous approach to design quality, and the ability to deliver impactful solutions. The position is based in San Jose, California. The stated pay range applies to the Bay Area, California: $231,500–$330,000 USD. Actual salary may vary based on location and job-related knowledge, skills, experience, and training. Incentive opportunities are also offered based on individual and company performance. Artificial intelligence is used to screen, assess, or select applicants. Applicants must be eligible for any required U.S. export authorizations.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
15 or more years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development.
Demonstrated technical leadership delivering complex digital subsystems or products from system architecture and microarchitecture through RTL, verification, integration, implementation, and post-silicon or hardware validation.
Deep hands-on expertise in Verilog and/or SystemVerilog RTL design, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design practices.
Experience with high-performance digital architectures, such as networking or packet-processing datapaths, offload or acceleration engines, PCIe/CXL, Ethernet, DDR/HBM memory subsystems, high-speed interfaces, or on-chip interconnect.
Strong understanding of performance, power, area, timing, bandwidth, latency, congestion, and reliability tradeoffs in advanced digital systems.
Experience leading design execution across multiple functional blocks or chip-level integration, including planning, risk management, schedule alignment, and technical prioritization.
Ability to collaborate and influence across architecture, RTL, verification, physical design, CAD, firmware/software, system validation, and product engineering organizations.
Strong written and verbal communication skills, including the ability to communicate architecture, design intent, technical risks, and recommendations to diverse audiences.
Eligibility for any required U.S. export authorizations.

Nice To Haves

Advanced degree in a relevant discipline.
Experience in FPGA architecture, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
Experience building or maintaining reusable design IP deployed across multiple products, programs, or technology nodes.
Experience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.
Proficiency in scripting and workflow automation using Python, Tcl, Perl, or shell.
Experience leading teams or serving as a senior technical mentor in a matrixed engineering environment.
Record of innovation through patents, publications, standards contributions, or technical thought leadership.

Responsibilities

Lead architecture, microarchitecture, and RTL development for complex FPGA, programmable SoC, and infrastructure-class subsystems, especially high-throughput datapaths, connectivity, interconnect, memory access, or programmable acceleration.
Define technical requirements, interfaces, architectural specifications, and implementation plans aligned with hardware, firmware, software, validation, and product objectives.
Drive technical tradeoffs involving performance, power, area, latency, bandwidth, reliability, scalability, cost, and schedule; use analysis to identify and mitigate execution risk.
Own critical blocks and subsystems through the development lifecycle, including RTL implementation, synthesis, integration, verification support, timing closure, bring-up, performance characterization, and issue resolution.
Establish and scale reusable design IP, coding standards, automation, and quality methodologies to improve engineering velocity, portability, predictability, and first-pass success.
Partner with architecture, design verification, physical design, DFT, CAD, firmware, software, emulation, FPGA prototyping, board, and post-silicon teams to maintain architectural intent through product delivery.
Lead resolution of complex cross-functional design and system issues, including root-cause analysis, debug strategy, and technical decision-making.
Provide technical mentorship and design leadership across teams through architecture reviews, code reviews, and constructive technical guidance.
Influence engineering roadmaps and collaborate with internal teams and external partners on IP, tools, and technology choices.