Senior Engineer, Physical Design (ASIC/SoC Place & Route) (Austin, TX)(5560)

TSMC•USA-Texas, TX

16d•$106,500 - $162,000•Hybrid

About The Position

As a Sr. Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff. You will be reporting to Manager of Advanced Chip implementation team at its Austin Design Center, Texas and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office.

Requirements

Master’s degree in Electrical/Computer Science Engineering with 7+ years of industry experience.
Netlist (or RTL)-GDS physical implementation experience
In depth knowledge of major EDA tools/design flows
Experience with TSMC N16 or below technology
Experience in block level implementation or chip integration and signoff
Experience in Perl/TCL language programming
Ability to work regularly at a Customer site in the North Austin, TX area

Nice To Haves

TSMC N5 and below technology
Low-power implementation methodology
Advanced timing signoff methodology
Able to independently complete Netlist-GDS P&R, signoff task
Proven record in multi-million gate design production tapeouts

Responsibilities

Complete entire physical implementation of the block level and tapeout production chip
Block level floorplan with the ability to analyze the quality of the floorplan
Customized Clock tree structure and Place & Route
Implement ECOs for timing closure
Signal EM/Noise and Power IR/EM analysis and fix
DRC/LVS/ERC/ANTENNA analysis and clean up
Physical verification sign off