Senior Digital Verification Engineer

Efficient Computer•San Jose, PA

20h

About The Position

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution. We are looking for an experienced Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Requirements

Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
Expertise in UVM-based testbench architecture and constrained-random verification methodology.
C/C++ experience for modelling or verification.
Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
Proven ability to debug complex simulation failures.
Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership.

Nice To Haves

Experience in Formal verification (JasperGold or similar).
Experience building or using AI Agentic flows for DV.
Software/Firmware based testing experience and working with software teams pre-silicon.
Post-silicon experience.
Understanding and experience in some of the following areas: processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
Power aware verification and UPF.

Responsibilities

Drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team.
Have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.