Senior Digital Design Verification Engineer - Hardware

NVIDIA•Santa Clara, CA

14h

About The Position

NVIDIA is hiring a Senior Digital Design Verification Engineer to verify the design and implementation of SerDes IPs. The technology supports gaming, artificial intelligence, deep learning, and autonomous driving, and will serve standard and proprietary high-speed protocols. The role develops and executes verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation. It includes bringing up and debugging verification environments on Cadence Palladium, preparing designs and testbenches for emulation, and running long-duration system scenarios. The engineer also develops C/C++ reference models and verification infrastructure, investigates failures across RTL and modeling environments, and collaborates with cross-functional teams to close coverage and deliver high-quality IP on schedule. Applications will be accepted at least until November 10, 2026. This posting is for an existing vacancy.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
At least 5 years of relevant design verification experience at the unit, subsystem, or SoC level.
Hands-on experience with Cadence Palladium or a comparable hardware emulation platform, including environment bring-up, regression execution, failure triage, and debugging.
Strong C/C++ programming skills, with experience developing verification models, test infrastructure, or hardware validation tests.
Strong SystemVerilog skills and experience building verification environments using UVM.
Experience with constrained-random stimulus, functional coverage, assertions, and coverage closure.
Strong debugging and analytical skills, including isolating emulation failures and reproducing issues in simulation.

Nice To Haves

Direct experience bringing up and debugging SerDes IP or subsystems on Cadence Palladium.
Experience adapting UVM testbenches, C/C++ models, and mixed-signal behavioral models for efficient emulation.
Experience developing SerDes RNM models and correlating their behavior with analog simulation results or silicon measurements.
Understanding of SerDes architectures, mixed-signal interfaces, calibration, adaptation, and link training.
Expertise in high-speed protocols such as PCI Express, USB, or SATA.

Responsibilities

Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.
Develop, bring up, and debug SerDes verification environments on Cadence Palladium, including preparing designs and testbenches for emulation and running long-duration system scenarios.
Run regressions, debug and triage failures, and reproduce issues in simulation as needed to support root-cause analysis and resolution.
Write and maintain C/C++ reference models, stimulus generators, checkers, and test code for simulation and emulation.
Investigate failures across RTL, verification infrastructure, C/C++ models, and RNM models, and collaborate with designers to resolve issues.
Work with architects, digital and analog designers, and pre- and post-silicon verification teams to define verification scope, close coverage, and deliver high-quality IP on schedule.