Senior Design Verification Engineer - Memory Controller IP
Rambus•Hillsboro, OR
•Hybrid
About The Position
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior/ Lead Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The successful candidate will participate in pre-silicon RTL Verification activities related to Memory Controller SoftIP development, on leading-edge DDR, HBM, and GDDR DRAM controller technologies.
Requirements
- Bachelors Degree or above in EE/CS
- minimum 7 years experience with HDL logic Design-Verification
- System Verilog testbench
- Verilog/System Verilog logic design/RTL fluency a must
Nice To Haves
- Pre-existing Experience / familiarity with DDR DRAM technology a strong preference
- Working experience with Python and TCL scripting languages preferred
Responsibilities
- Testbench and test sequence development for verification of new controller technologies and features
- Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
- Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
- Development & support of Verification environment scripting and capabilities
Benefits
- base salary
- bonus
- equity
- matching 401(k)
- employee stock purchase plan
- comprehensive medical and dental benefits
- time-off program
- gym membership
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Upload and Match Resume
What This Job Offers
Job Type
Full-time
Career Level
Senior
