IP Design Verification Engineer

Intel•Hillsboro, CA

1d•Hybrid

About The Position

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's lives. Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products ? If so, come join us to do something wonderful. As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple Server SoCs. A successful candidate will have proven experience demonstrating the following skills and behavioral traits: Analytical and problem-solving skills Verbal/written communication skills Effective team player with continuous learning mindset Willingness to balance multiple tasks Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process

Requirements

Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
IP or SoC verification experience using System Verilog/UVM
Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
Implementation of verification environments that include use of constrained-random stimulus
Code/Functional Coverage analysis
Writing System Verilog Assertions (SVA)

Nice To Haves

Mixed-Signal Verification Experience with UCIe or PCIe or I/O

Responsibilities

Test bench development, directed/constrained random test generation in UVM
Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
Run RTL and gate level functional verification, debug failures, and analyze coverage
Support mixed-signal verification using Verilog models of analog IP