Senior ASIC Physical Design Engineer
About The Position
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips.
Requirements
- Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience, or Master’s degree in Electrical or Computer engineering and 4+ years of ASIC relevant experience, or PhD in Electrical or Computer engineering + 1 year of ASIC relevant experience
- Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.
Nice To Haves
- Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment.
- Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
- Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
- Experience with custom clock (H-Tree or Mesh) at chip level.
- Experience with Python and usage of AI tools by giving accurate prompts
Responsibilities
- Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
- Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
- Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
- Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime.
- Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
- Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
- Evaluate and implement new timing methodologies; provide creative debugging solutions.
- Contribute to best practices and drive methodology alignment across projects.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
