Senior ASIC Display Design Engineer

Qualcomm•Markham, ON

1d•CA$104,900 - CA$154,900•Onsite

About The Position

The successful candidate will join the Display IP Design team in developing leading edge display solutions in Qualcomm SoC's. We are looking for individuals that possess internal drive and keen desire to learn on the job. You will work within a multi-disciplinary, multi-site team of architects, designers and verification engineers and will be responsible for the IP design development and integration within the display sub-system. This is a new position.

Requirements

Legally permitted to work on-site in Canada
2+ years of ASIC design experience.
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.

Nice To Haves

Prior experience delivering Verilog and System Verilog RTL
Detail oriented with strong analytical and debugging skills
Strong communication (written and verbal), collaboration, and specification skills
Practiced design knowledge working with some of the following concepts: Clock domain crossing and reset architecture, Machine Learning HW development, FIFOs implementation, Bus implementation/verification techniques, Memory selection and control, High speed and low power design optimization, Bus interface protocols (AHB, AXI)
Experience with some of the following: Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium), Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.), Scripting languages (PERL, Python, TCL, C, etc.), Power Intent and Analysis: UPF, CLP, PTPX, PowerPro, Synthesis: DCG/NXT, FC, Static Timing: Primetime, Formal Verification: Conformal, Formality

Responsibilities

Develop of Micro-Architecture and specification based on high level design requirements
Develop RTL design that meets required performance and is optimized for Area and Power
Integrate pre-verified sub-IPs to build up larger functionality
Flow bring up and report analysis for Linting, RTL Synthesis, CLP, CDC
Work closely with verification team to define testplan, debug regression, analyze coverage reports
Develop SVA assertions for white box verification for formal verification
Effective communication across teams, multitasking and well-planned execution of the tasks.