ASIC Design Engineer

NVIDIA•Santa Clara, CA

1d•$116,000 - $189,750

About The Position

NVIDIA's VLSI team transforms groundbreaking GPU and accelerator architectures into production silicon at the world’s most advanced process nodes. Our team drives IP design, and verification for chips of unmatched complexity — billions of transistors pushing the limits of performance and power efficiency. Unlike typical VLSI roles, engineers here directly shape products that define the state of the art in AI, HPC, and autonomous systems, working at a pace and scale few organizations can match. If you want your implementation expertise to have outsized real-world impact, this is the place.

Requirements

MS in Electrical or Computer Engineering (or equivalent experience).
3+ years of experience.
Strong background in advanced submicron process issues.
Deep understanding of the build and verification of both conventional cell libraries and custom ROMs.
Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools.
Experience with running EM/IR, aging, noise, margin, and high sigma variation simulations.
Hands-on experience of DRC/LVS debug.
Experience of designing and optimizing flip flops, level shifters, latches, and/or custom ROMs, register files, SRAM.
Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods/algorithms a certain plus.

Nice To Haves

Exposure to standard cell, memory, or custom circuit development would be beneficial.
Experience with RTL, logic synthesis, and familiarity with place and route is preferred.
Prior leadership experience is advantageous.
Good interpersonal skills, quick learner, proactive, innovative, highly motivated, and committed.

Responsibilities

Work on the cutting edge standard cell libraries and/or custom ROM (Read Only Memory) modules in deep submicron technologies.
Drive the concepts of the transistor level standard cell circuit design, modeling and performance analysis process.
Lead the function and feasibility verification of new ROM designs and set up new design flows.
Provide creative insights to support and enhance existing tools and flows and develop new simulations to perform design margin evaluations.
Collaborate with multi-functional teams regarding opportunities to improve standard cell develop.
Improve on our quality checks on the libraries.