Senior Analog Engineering Manager

Renesas Electronics•Johns Creek, GA

About The Position

Renesas is seeking a Senior Analog Engineering Manager to lead development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. The role combines deep expertise in high-speed memory interfaces with people leadership and program ownership. The manager will lead end-to-end delivery of high-performance, low-power DDR PHYs from architecture through silicon bring-up and help shape the roadmap for DDR6-class signaling and architecture. The manager will guide DDR5 PHY architecture, design, and implementation, contribute to DDR6-ready architectures, and oversee critical analog and mixed-signal blocks. They will lead post-silicon bring-up, characterization, debug, yield improvement, and lab and customer-system correlation. The role also includes building and mentoring an engineering team, setting technical direction and development plans, hiring and scaling the team, and owning DDR5/DDR6 execution across schedule, quality, and risk. The position partners with digital PHY and controller teams, SoC integration and system architecture, package, PCB, SI/PI, validation, product, program management, customers, foundries, IP vendors, and standards bodies. It establishes design and signoff methodologies, improves simulation accuracy, mixed-signal verification, and silicon-debug efficiency, and leads DDR5 sustainment and DDR6 roadmap planning. Renesas describes its culture as Transparent, Agile, Global, Innovative, and Entrepreneurial, and offers a competitive benefits package; further information is provided during the hiring process.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering; a PhD is preferred.
12+ years of experience in analog/mixed-signal IC design, with a deep focus on high-speed memory interfaces.
5+ years of people-management and technical-leadership experience.
Proven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5.
Strong expertise in high-speed IO design and signal integrity.
Strong expertise in PLL/DLL and low-jitter clocking architectures.
Strong expertise in mixed-signal verification and silicon validation.
Strong expertise in advanced CMOS process considerations for IOs.
Strong written and verbal communication skills across technical and executive audiences.
High technical credibility and ability to engage deeply in technical work.
Execution mindset, disciplined risk management, mentoring and team-building ability, and a strategic, roadmap-driven approach.
Ability to balance hands-on engagement with organizational leadership.

Nice To Haves

Direct involvement in DDR6 architectural studies or early-stage development.
Experience at advanced nodes (7nm, 5nm, and below).
Background in multi-generation memory PHYs or scalable PHY platforms.
PhD in Electrical Engineering.

Responsibilities

Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.
Provide technical oversight for high-speed TX/RX datapaths, equalization, termination and training circuits, DLL/PLL-based clocking, voltage and reference generation, and power-aware IO design.
Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for DDR5/DDR6 data rates.
Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction.
Lead post-silicon bring-up, characterization, debug, yield improvement, and lab and customer-system correlation.
Build, lead, mentor, hire, onboard, and scale a team of analog and mixed-signal designers.
Set technical direction, performance expectations, and development plans for senior and principal engineers.
Own DDR5/DDR6 PHY execution while balancing schedule, quality, and risk.
Partner with digital PHY and controller teams, SoC integration and system architecture, package, PCB, SI/PI, validation, product, program management, and customers.
Interface with foundries, IP vendors, and standards bodies to support delivery and future readiness.
Establish design and signoff methodologies for next-generation high-speed PHYs.
Improve simulation accuracy, mixed-signal verification, and silicon-debug efficiency.
Lead DDR5 sustainment and DDR6 technology roadmap planning, including architectural trade-offs and scaling strategies.
Anticipate challenges related to data-rate scaling, power efficiency, and advanced process technologies.
Lead teams delivering multiple concurrent tape-outs.