Senior AI Performance Architect

Qualcomm•San Diego, CA
•$126,700 - $190,100

About The Position

Qualcomm Technologies, Inc. is seeking an AI Accelerator Architecture Engineer to help advance functional, performance, and power capabilities in hardware for state-of-the-art AI training. The role supports AI inference and training systems that scale across accelerators, servers, and racks, and contributes to Qualcomm’s work to expand power-efficient AI across mobile devices, edge and data-center systems, vehicles, and other connected devices. The AI Architecture team includes specialists in software architecture, algorithm development, kernel optimization, hardware accelerator block architecture, and SoC design. The successful candidate will contribute across one or more of these areas, helping define hardware and software architectures for increasingly large AI models. The work includes evaluating accelerator designs, developing architectural enhancements, modeling performance, and assessing performance, area, and power trade-offs for future hardware and machine-learning algorithms.

Requirements

  • Master's degree in Computer Science, Engineering, Information Systems, or a related field.
  • 3+ years of Hardware Engineering experience defining architectures for GPUs or accelerators used to train AI models.
  • In-depth knowledge of NVIDIA/AMD GPU capabilities and architectures.
  • Knowledge of LLM architectures and their hardware requirements.
  • Alternatively, the minimum qualifications specify a bachelor's degree in a relevant field and 2+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related experience; a master's degree in a relevant field and 1+ year of such experience; or a PhD in a relevant field.

Nice To Haves

  • Knowledge of computer architecture, digital circuits, and hardware simulators.
  • Knowledge of communication protocols used in AI systems.
  • Knowledge of Network-on-Chip (NoC) designs used in System-on-Chip (SoC) designs.
  • Understanding of memory technologies used in AI systems.
  • Experience modeling hardware and workloads to estimate performance and power.
  • High-level hardware modeling experience.
  • Knowledge of AI training systems such as NVIDIA DGX and NVL72.
  • Experience training and fine-tuning LLMs with distributed training frameworks such as DeepSpeed and FSDP.
  • Knowledge of front-end ML frameworks such as TensorFlow and PyTorch for training ML models.
  • Strong written and verbal communication skills.
  • Detail-oriented, with strong problem-solving, analytical, and debugging skills.
  • Ability to learn, think, and adapt in a fast-changing environment.
  • Ability to code in C++ and Python.
  • Knowledge of a variety of ML model classes, such as CNNs and RNNs.

Responsibilities

  • Understand ML network design trends through customer engagements and academic research, and determine their implications for software and hardware design.
  • Work with customers to determine hardware requirements for AI training systems.
  • Analyze current accelerator and GPU architectures.
  • Architect enhancements for efficient AI model training.
  • Design flexible computational blocks that support floating-point, fixed-point, and microscaling data types; multiple precisions from 32-bit through 1-bit; and dense and sparse GEMM and GEMV operations.
  • Design memory technologies and subsystems to address capacity and bandwidth requirements, including compute-in-memory and compute-near-memory approaches.
  • Design scale-out and scale-up architectures, including switches, NoCs, and co-design with communication collectives, optimized for power.
  • Perform competitive analysis.
  • Co-design hardware with software and generative AI/LLM requirements.
  • Define performance models to evaluate the effectiveness of architecture proposals.
  • Predict pre-silicon performance for various ML training workloads.
  • Analyze performance, area, and power trade-offs for future hardware and software ML algorithms, including the impact of SoC components such as memory and buses.

Benefits

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus).
  • Competitive benefits package designed to support employees at work, at home, and at play.
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