Semiconductor Device Modeling Engineer

Intel Corporation•Hillsboro, OR

7d•$173,660 - $330,340•Onsite

About The Position

The Semiconductor Device Modeling Engineer will join Intel’s Compact Device Modeling Group (CDMG), part of the Design Technology Platform organization. CDMG supports Intel Foundry customers by co-optimizing process technology and enabling design teams to develop products for data-centric applications. The role supports compact modeling activities for Intel’s new technologies, including advanced transistor technologies such as FinFET and GAAFET.

Requirements

A master’s degree in Electrical Engineering or a related discipline and at least 5 years of industry experience in the semiconductor field, or a Ph.D. in Electrical Engineering or a related discipline and at least 3 years of semiconductor industry experience.
At least 3 years of hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes, such as FinFET or GAA.
Proficiency with extraction tools such as ICCAP or MBP and commercial simulators such as HSPICE or Spectre.
Strong background in IV/CV fitting, model retargeting, and corner/statistical variation modeling.
Experience developing LLE models for FinFET or GAAFET technologies.
Skill in Python scripting for automation and documentation.

Nice To Haves

A Ph.D. in Electrical Engineering or a related discipline and 8 or more years of semiconductor industry experience.
Expertise in layout-dependent effects (LDE) and their impact on circuit performance.
Experience modeling with the Open Model Interface (OMI).
Strong understanding of process flow, layout, and basic circuit design and simulation.
Experience modeling self-heating effects and their influence on device and circuit performance.
Experience developing methodologies for device targeting and benchmarking circuits, including corners and statistical variation models.
Demonstrated technical leadership and ability to collaborate across multiple teams and geographies.
Experience with machine learning algorithms and their application to data analysis and compact model development.

Responsibilities

Support compact modeling activities for Intel’s new technologies.
Develop LLE models for FinFET or GAAFET technologies.
Perform transistor model extraction, IV/CV fitting, model retargeting, and corner and statistical variation modeling.
Use scripting to automate and document modeling work.