RTL Intern
Etched•San Jose, CA
•Onsite
About The Position
As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.
Requirements
- Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Able to learn quickly about transformers and other aspects of modern artificial intelligence
Nice To Haves
- Familiarity with modern ML and LLM model architectures
- Familiarity with numerical representations and functions
- Familiarity with clocking and reset schemes
- Ability to program with Python or another scripting language
Responsibilities
- Help design microarchitecture
- Implement logic in verilog
- Work with cutting-edge machine learning architectures
- Contribute to RTL block development
- Participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback
Benefits
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Direct mentorship from industry leaders and world-class engineers
- Opportunity to work on one of the most important problems of our time
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What This Job Offers
Career Level
Intern
Education Level
No Education Listed
