RTL SoC Design Intern
About The Position
Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems. Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21. This is a chance to get hands-on experience building a next-generation SoC architecture from the ground floor, working directly alongside our hardware team as we bring supercomputer technology to the Edge. You'll support the SoC design team with subsystem development, third-party IP integration, and PPA (power, performance, area) optimization for Quadric's GPNPU platform — gaining exposure to real front-end design and integration methodologies, and working closely with the architects who define the chip. Our preference is for this internship to be based out of our Burlingame, California office. Candidates should be based in the Bay Area or able to relocate for the internship period and available to work on site.
Requirements
- Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Familiarity with SoC/ASIC front-end design concepts.
- Proficient in SystemVerilog or Verilog.
- Prepared to collaborate with architects and designers on subsystem development and integration tasks.
- Demonstrated capability in problem-solving, debugging, and clear technical communication.
Nice To Haves
- Coursework or project experience with computer architecture, low-power design, or RTL design.
- Exposure to logic synthesis, FPGA design, or performance modeling.
- Adept with scripting languages like Python and using LLMs to get things done
Responsibilities
- Support SoC Subsystem Development: Help design and integrate SoC-level subsystems, working alongside engineers integrating third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
- Contribute to documentation of SoC architecture and application requirements.
- Support PPA Optimization: Assist in analyzing and optimizing Power, Performance, and Area (PPA) at the SoC level.
- Get exposure to low-power digital design techniques and timing closure work across front-end stages.
- Collaborate Across the Team: Work closely with SoC architects and designers to understand design intent and integration requirements.
- Communicate findings, blockers, and technical questions clearly to the team.
Benefits
- Catered lunch each day in our office
- Downtown Burlingame office location, close to shops, cafes, and local amenities
- A work culture focused on innovative disruption
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What This Job Offers
Career Level
Intern
Education Level
No Education Listed
